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Author SHA1 Message Date
Rebecca Mckeever
27037efcfd panvk: Add STORAGE_IMAGE_BIT feature for formats supporting sampled images 
All formats that support sampled images should also be suitable for
storage images.

Fixes: d970fe2e ("panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs")

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33459>
 2025-03-06 14:45:16 +00:00
Valentine Burley
90f33b217d panfrost/ci: Pin g610-gl job to 4GB DUTs 
Use exclusively the 4GB devices for the panfrost-g610-gl job, to preserve
the 8GB+ devices for the Vulkan jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33865>
 2025-03-06 13:48:36 +00:00
Valentine Burley
dceb9a1a9b panfrost/ci: Shorten Piglit job names 
Drop extra gl and gles labels from the job names.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33865>
 2025-03-06 13:48:35 +00:00
Valentine Burley
b310a4a13d panfrost/ci: Add a Piglit job on G57 
We have more than enough devices available to add a new Piglit job on the
new mt8195-cherry-tomato-r2 device.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33865>
 2025-03-06 13:48:35 +00:00
Valentine Burley
815295e7bb panforst/ci: Migrate the G57 GL job to MT8195 
Migrate the panfrost-g57-gl job to a new device in LAVA,
mt8195-cherry-tomato-r2. This DUT is faster than the
mt8192-asurada-spherion-r0 device it replaces.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33865>
 2025-03-06 13:48:35 +00:00
Vasily Khoruzhick
dd765da872 lima: ppir: try inserting nodes into successor instr for uncond branch 
It is safe to attempt inserting a node into the same instruction as
successor if successor is an unconditional branch.
ppir_instr_insert_node() will take care of conflicts with ALU_COMBINE
slot

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33754>
 2025-03-06 13:25:40 +00:00
Vasily Khoruzhick
fa9ddbe82b lima: ppir: optimize branches 
Implement 2 optimizations for branches:

1) if unconditional branch target is a block that only has
   unconditional branch, propagate the target
2) optimize following contruction:
   block 1:
   ...
   if (cond) block 3
   block 2:
   branch block N
   block 3:
   ...

   into

   block 1:
   ...
   if (!cond) block N
   block 2:
   block 3:
   ...

Note: optimization 1) significantly improves runtime of if ladders, but
it is not visible in shader-db because we do not track shortest/longest
path and it doesn't always create dead code (usually just a single
instruction)

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33754>
 2025-03-06 13:25:40 +00:00
Vasily Khoruzhick
69b119bc00 lima: ppir: assign actual index to discard block 
Discard block is always added to the block list after translation from NIR,
so we can just assign it an index that equals to block list size.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33754>
 2025-03-06 13:25:40 +00:00
Samuel Pitoiset
2a56afed8d radv: switch to device address from vk_buffer 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:01 +00:00
Faith Ekstrand
c99039e189 vulkan/meta: Use vk_buffer.device_address directly 
This saves us jumping through an entrypoing just to fetch a uint64_t.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:01 +00:00
Faith Ekstrand
b808277d09 hk: Use the new buffer device address infrastructure 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:01 +00:00
Faith Ekstrand
8ca0531485 panvk: Use the new buffer device address infrastructure 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:00 +00:00
Faith Ekstrand
7900ff5c56 nvk: Use the new buffer device address infrastructure 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:00 +00:00
Faith Ekstrand
73da18b956 vulkan: Add device address helpers to vk_buffer 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
 2025-03-06 09:46:00 +00:00
Job Noorman
c44243099f ir3: lower immediates to const regs in preamble on a7xx 
On a7xx, const registers should be loaded via the preamble instead of
uploaded by the driver to the const state. This commit implements this
by adding a new pass that emits the consts created by ir3_cp to a
sequence of stc instructions in the preamble.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
fbe8fc0dae ir3: fix max const size calculation for the binning pass 
The binning pass should never exceed the const size of the non-binning
pass.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
434b82469f ir3: make const_imm_index_to_reg helper public 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
68ab25e6d4 ir3: split immediate state from rest of const state 
On a7xx, the immediates that get promoted to const registers will be
initialized in the preamble instead of being part of the const state. So
technically, we won't need the immediate state that is part of the const
state anymore on a7xx. However, it is still a convenient place for
ir3_cp to store the immediates that should be promoted to const
registers before they are lowered to the preamble.

This causes one issue: the binning pass isn't allowed to modify the
const state while it's perfectly fine for it to use different immediates
compared to the non-binning pass on a7xx. Even pre-a7xx this is fine as
long as the size of the immediate buffer is the same.

To allow the binning pass to modify its immediate state while keeping
its const state immutable, this commit moves the fields related to
immediates into a new struct. Runtime checks are added to enforce that
the size of the immediate buffer is the same for the binning and
non-binning variant pre-a7xx.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
f9fc0fc8fd ir3/sched: handle dependencies between stc and const reads 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
0f6ec14925 ir3: fix false dependencies of rpt instructions 
When merging multiple instructions into one rpt instruction, the false
deps of the rpt instruction should be the union of the false deps of its
parts.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4c4366179b ("ir3: add post-RA pass to merge repeat groups into rptN instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:54 +00:00
Job Noorman
62d2069617 ir3: add helper to create STC 
Creating STC is complicated since we might need to use a1.x for
addressing. Extract the current code into a helper so that it can be
used elsewhere.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:53 +00:00
Job Noorman
3186443057 ir3: remove hash table for a1.x 
Removing duplicates is now supported by ir3_cse so the hash table is
unnecessary. Removing it will make it easier to create instructions
using a1.x without having access to ir3_context.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:53 +00:00
Job Noorman
06978e0c0c ir3/cse: add support for mov a0.x/a1.x 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:53 +00:00
Job Noorman
ac18eccd74 ir3: add ir3_cursor_current_block helper 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
 2025-03-06 08:47:53 +00:00
Lorenzo Rossi
69982e6f2f nak: Flatten AttrAccess into instructions 
The AttrAccess structure provided inputs for similar instructions, some
inputs were used only in a subset of instructions, needing asserts and
dummy values.
This commit flattens the struct directly in the instructions removing
the unused fields and cleaning up the code.

Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33899>
 2025-03-06 05:29:56 +00:00
Eric Engestrom
2c034470ed docs: add sha sum for 25.0.1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904>
 2025-03-06 04:07:22 +00:00
Eric Engestrom
4fb7c57e29 docs: add release notes for 25.0.1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904>
 2025-03-06 04:07:22 +00:00
Eric Engestrom
487af01696 docs: update calendar for 25.0.1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904>
 2025-03-06 04:07:20 +00:00
Corentin Noël
24dbc278f0 tnn: nir: Don't use deprecated NIR_PASS_V macro anymore 
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
 2025-03-06 03:29:21 +00:00
Corentin Noël
acd5f2971a ntt: nir: Don't use deprecated NIR_PASS_V macro anymore 
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
 2025-03-06 03:29:20 +00:00
Corentin Noël
eb1274ef08 nir: Add bool return value to nir_legacy_trivialize(..) 
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
 2025-03-06 03:29:20 +00:00
Corentin Noël
8eae89f3f0 virgl: nir: Don't use deprecated NIR_PASS_V macro anymore 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
 2025-03-06 03:29:20 +00:00
Christian Gmeiner
71e2ddcede etnaviv/ci: Add gles2 run for GC3000 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33838>
 2025-03-06 03:09:12 +00:00
Assadian, Navid
9a88afecbd amd/vpelib: More parameters to the segmentation process and introduce validation hook 
Generalization for the following:
1. pass in the scaler output alignment requirement to segment number determination function
2. parameter validation hook

Signed-off-by: Navid Assadian <Navid.Assadian@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
 2025-03-06 02:11:53 +00:00
Zhao, Jiali
37c244998a amd/vpelib: Fix studio output CSC 
Fix studio output CSC.

Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
 2025-03-06 02:11:53 +00:00
Visan, Tiberiu
da04cbca66 amd/vpelib: Apply normalization for full range 
[WHY]
The full range needs to have the same brightness normalization like the
studio range.

[HOW]
Apply the same normalization.

Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Tomson Chang <Tomson.Chang@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
 2025-03-06 02:11:53 +00:00
Visan, Tiberiu
b3d43cea08 amd/vpelib: Fix studio range 
[WHY]
Studio signal has an offset.

[HOW]
Subtract that offset.

Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
 2025-03-06 02:11:53 +00:00
Leder, Brendan Steve
69c331e2c0 amd/vpelib: Reformat index variables and update enum 
Reformat index variables to indicate loop specifics and update enum to match formatting guide.

Signed-off-by: Brendan Steve Leder <Brendansteve.Leder@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
 2025-03-06 02:11:53 +00:00
Vasily Khoruzhick
6528ee4228 lima: ppir: reuse load_temp/store_temp nodes if possible 
Currently spilling code operates on individual ops rather than on
instructions, and as a result it may create a redundant load_temp op if
an instruction references spilling register several times.

Similarly, it creates multiple stores if there are multiple ops in the
instruction that write different components of the register.

Check whether the instruction already contains a necessary load_temp or
store_temp and reuse it if possible.

shader-db:

total instructions in shared programs: 27718 -> 27673 (-0.16%)
instructions in affected programs: 2786 -> 2741 (-1.62%)
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.50 x̃: 1
helped stats (rel) min: 0.39% max: 5.33% x̄: 2.05% x̃: 0.80%
95% mean confidence interval for instructions value: -3.70 -1.30
95% mean confidence interval for instructions %-change: -3.09% -1.01%
Instructions are helped.

total loops in shared programs: 4 -> 4 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 390 -> 381 (-2.31%)
spills in affected programs: 145 -> 136 (-6.21%)
helped: 9
HURT: 0

total fills in shared programs: 1210 -> 1174 (-2.98%)
fills in affected programs: 149 -> 113 (-24.16%)
helped: 9
HURT: 0

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33753>
 2025-03-06 01:48:55 +00:00
Mike Blumenkrantz
7200cf8827 radv: don't unnecessarily flag prolog recalc when binding VBOs 
another 25% for vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
4f71370830 radv: get vbo info directly into dgc upload 
don't need this memcpy

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
b78835de13 radv: move non_trivial_format calc to dynamic VI bind 
this otherwise gets pointlessly recalculated on every draw when a VBO changes

another 10% for vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
42db08c275 radv: split out dynamic vertex input descriptor writing 
~25% boost to vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
22434edefc radv: inline some vertex descriptor functions 
+5-7% in vkoverhead 16

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
00f51f7215 radv: eliminate a memset in radv_get_vbo_info() 
very minor perf cost

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
e2ccd638a8 radv: roll line topology dynamic state changes into existing rast samples flag 
this eliminates uploading rast samples whenever prim type changes even
when rast samples will not be changed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
b2123314bd radv: store vertex prolog simple input check to cmdbuf on vs bind 
no need to check this again and again

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
881d94a40a radv: store num_attributes to shader info 
this eliminates a util_last_bit from the prolog hotpath

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
d40dd4bfb7 radv: rewrite radv_get_line_mode() conditional 
this was weirdly hard to parse

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
 2025-03-06 01:26:02 +00:00
Alyssa Rosenzweig
6c24ac7d21 panfrost: clean up CL meson rules 
we shouldn't need any of this anymore. I cleared out similar gunk from Asahi, we do the same for Panfrost here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
 2025-03-06 00:43:59 +00:00