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Author SHA1 Message Date
David Heidelberg
79f7882fc6 ci: add quirk for GitLab assuming changes is always true for scheduled runs 
Sadly GitLab CI always evaluate `rules:changes` as true, when running
scheduled runs. So we have to add explicit condition to ignore it there.

Every line using `rules:changes` has to have following condition
ignoring "schedule" runes.

Cc: mesa-stable
Reported-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24051>
 2023-07-17 18:12:27 +00:00
Alyssa Rosenzweig
16b080b5d8 ir3: Use nir_lower_tess_coord_z 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24159>
 2023-07-17 17:31:52 +00:00
Alyssa Rosenzweig
2c8f884103 r600: Use nir_lower_tess_coord_xy 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24159>
 2023-07-17 17:31:52 +00:00
Alyssa Rosenzweig
4f0f76346e nir: Add nir_lower_tess_coord_z pass 
Lowers tess_coord to tess_coord_xy and math. Based on ir3's version.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24159>
 2023-07-17 17:31:52 +00:00
Alyssa Rosenzweig
9109830bb0 nir: Promote tess_coord_r600 to tess_coord_xy 
This intrinsic (vec2 tess_coord) is generally useful for non-r600 backends.
Promote it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24159>
 2023-07-17 17:31:52 +00:00
Eric Engestrom
74f8956f27 ci: replace copy of nouveau rules with reference 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24190>
 2023-07-17 16:11:42 +00:00
Marek Olšák
005ffbe4b7 freedreno,lima,zink: update CI fixes and flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24165>
 2023-07-17 15:36:48 +00:00
Marek Olšák
c97961a855 mesa: fix 38% decrease in display list performance of Viewperf2020/NX8_StudioAA 
It happened because glCallList was restoring varying_vp_inputs, which
caused every glCallList to process the state change again.

This loosely reverts commit 3a294ff01f
"mesa: move the _mesa_set_varying_vp_inputs call to where the state changes".

Fixes: 3a294ff01f - "mesa: move the _mesa_set_varying_vp_inputs call to where the state changes"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24165>
 2023-07-17 15:36:47 +00:00
Guilherme Gallo
701b035179 bin/ci: Ensure that all jobs have nodes in DAG 
Some automatic jobs, such as 'rustfmt' and 'clang-format', are skipped
during the graph sweep because their parents are already included in the
node set.

This commit ensures all visited jobs are in DAG and fixes iteration
modification using deepcopy.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9376

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24176>
 2023-07-17 15:34:11 +00:00
Rhys Perry
5e4029bfe5 nir/tests: add test for unsigned_upper_bound with loop header phis 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23990>
 2023-07-17 14:45:21 +00:00
Rhys Perry
1139d870f3 nir/unsigned_upper_bound: fix phi(bcsel) 
This was looking at the wrong sources. src0 is the condition.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Fixes: 72ac3f6026 ("nir: add nir_unsigned_upper_bound and nir_addition_might_overflow")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23990>
 2023-07-17 14:45:21 +00:00
Leo Liu
34c4a195f9 radeonsi: add AV1 profile to supported profile 
With fully supported profile, we will get info based on querying to
the kernel.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24161>
 2023-07-17 14:25:12 +00:00
Rohan Garg
36d4e83299 intel/perf: add perf query support for Intel Raptorlake 
Fixes: 4e0eca7dc3 ("intel/dev: Add device info for RPL")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24180>
 2023-07-17 13:56:02 +00:00
Marek Olšák
6cda08416b glthread: determine global locking once every 64 batches to fix get_time perf 
This mitigates a large perf degradation when the clock source is HPET instead of TSC.
Just call get_time less frequently.

Fixes: 3ed141e9 - glthread: add a heuristic to stop locking global mutexes with multiple contexts
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8910

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24168>
 2023-07-17 13:16:47 +00:00
Rhys Perry
d4b211bf1b ac/nir: always round cube array layers 
It seems this is still necessary if conformant_trunc_coord=true.

Fixes various dEQP-VK.texture.shadow.cube_array.* and
dEQP-VK.glsl.texture_functions.texture*samplercubearray* failures with
conformant_trunc_coord.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: 23.2 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24137>
 2023-07-17 12:17:22 +00:00
Rhys Perry
e02f8b62af radv: don't unset TRUNC_COORD if conformant_trunc_coord=true 
This isn't necessary.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24137>
 2023-07-17 12:17:21 +00:00
Rhys Perry
436df35c17 radv: add conformant_trunc_coord to cache UUID 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24137>
 2023-07-17 12:17:21 +00:00
Rhys Perry
0cb26f31fe ac/llvm: skip ballot zext for 32-bit dest with wave32-as-wave64 
NGG lowering can ballots with a 32-bit destination even if the ballot bit
size is 64.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24140>
 2023-07-17 11:21:35 +00:00
Rhys Perry
47c9dea6ac ac/llvm: fix wave32 ac_build_mbcnt_add with 64-bit mask 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24140>
 2023-07-17 11:21:35 +00:00
Rhys Perry
7a199a051e radv: fix radv_get_ballot_bit_size with CS 
For wave64-as-wave32, this would return 32.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24140>
 2023-07-17 11:21:34 +00:00
Rhys Perry
85d1159a2a ac/llvm: fix AC_TM_CHECK_IR 
This was using the wrong pass.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: 3f272fd15e ("ac/llvm: fix build with LLVM 17")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24140>
 2023-07-17 11:21:34 +00:00
Lucas Stach
f7c74e35ee etnaviv: remove bogus comment about replacing resource storage 
While we might want to employ this orphaning trick one day to avoid stalls
on busy resources it's certainly not as easy as the comment implies, as
this would involve changing all relocs in cached state objects referencing
the resource.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
4b17bab6b4 etnaviv: remove always true assert in etna_transfer_unmap 
The level parameter is already checked in etna_transfer_map, so there
is no way that the unmap could end up violating the assert.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
ab1d4ac338 etnaviv: remove superfluous braces 
etnaviv gernerally uses the style where no braces are used if the
statement inside a conditional clause fits on a single line. Remove
some superfluous braces to be more consistent.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
bee2a84657 etnaviv: move buffer range tracking into the PIPE_MAP_WRITE clause 
Move the valid buffer range tracking next to all the other things we
do on write mapping.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
e1c00ce5c9 etnaviv: remove huge outdated comment 
The comment makes it seem like we don't track resource status, which might
have been the case long ago, before the driver was even merged in upstream
Mesa, but is definitely no longer true. The kernel driver keeps track of
submitted work on BOs, the Mesa driver properly tracks unsubmitted usages
of any resource.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
6638ba513b etnaviv: reword comment about staging resource usage 
The current wording isn't really accurate. It talks about depth surfaces,
while in reality any surface used by the PE can have TS allocated. Also
with compression the TS doesn't only track "holes" aka clear tiles, but
instead carries the compression tags.

Reword to hopefully match reality a bit better.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
f6222a4b92 etnaviv: check for valid TS as condition to create the staging resource 
Presence of the TS buffer doesn't necessarily mean that there is valid
TS information that we need to take into account. This is pretty harmless
as the blit into the staging resource will just ignore invalid TS data
and most TS enabled resources are (super-)tiled anyways, which we will
handle with a staging resource nonetheless, but better not keep this bad
example around and replace with the appropriate check.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
78a999ecfa etnaviv: don't allocate full resource as transfer staging 
The transfer only targets a specific level of a resource, so we don't
need to allocate all potential resource levels for the staging resource,
but instead shrink the allocation to a single level.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Lucas Stach
8c8741a17e etnaviv: split etna_copy_resource_box levels parameter in src/dst 
Allow to copy between different level in the source and destination
resource.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24164>
 2023-07-17 09:27:13 +00:00
Rohan Garg
07a9585898 iris: fix iris for WA 16013000631 
iris needs to emit a PIPE_CONTROL_INSTRUCTION_INVALIDATE for the
aforementioned WA.

Fixes: 83716b08c ('iris: migrate WA 14013910100 to use the WA framework')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24171>
 2023-07-17 09:03:21 +00:00
Lionel Landwerlin
a303ff6684 isl: add a tool to query surface parameters 
$ ./build/src/intel/isl/isl_query -p dg2 -w 128 -h 64 -l 4
Surface parameters:
  dim:                 2d
  dim_layout:          0
  msaa_layout:         0
  tiling:              64
  format:              R8G8B8A8_UNORM
  img_align_el:        128x128x1
  logical_level0_px:   128x64x1x1
  phys_level0_sa:      128x64x1x1
  levels:              4
  samples:             1x
  size_B:              131072
  alignment_B:         65536
  row_pitch_B:         512
  array_pitch_el_rows: 256
  tile_info:
    tiling:             64
    format_bpb:         32
    logical_extent_el:  128x128x1x1
    phys_extent_B:      512x128 = 65536

$./build/src/intel/isl/isl_query -p skl -w 128 -h 64 -l 4 -f R8G8B8_UINT
Surface parameters:
  dim:                 2d
  dim_layout:          0
  msaa_layout:         0
  tiling:              Y0
  format:              R8G8B8_UINT
  img_align_el:        16x4x1
  logical_level0_px:   128x64x1x1
  phys_level0_sa:      128x64x1x1
  levels:              4
  samples:             1x
  size_B:              36864
  alignment_B:         4096
  row_pitch_B:         384
  array_pitch_el_rows: 96
  tile_info:
    tiling:             Y0
    format_bpb:         8
    logical_extent_el:  128x32x1x1
    phys_extent_B:      128x32 = 4096

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24142>
 2023-07-17 08:05:21 +00:00
David Heidelberg
dfd96fac41 ci/freedreno: add another a530 flakes 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:24 +02:00
David Heidelberg
f952756d1e ci/freedreno: fix unexpectedpass flake on a630 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:24 +02:00
David Heidelberg
5b3cccaf63 ci/lima: EGL testing was disabled when fp16 fail was removed 
fd4d0e1cc2 ("st/mesa: Set gl_config.floatMode based on color_format"),
fixed this functionality across multiple drivers, but EGL testing on
Mali was disabled back then, theofore it still fails here.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:24 +02:00
David Heidelberg
87439a8c71 ci/radeonsi: stoney arb_timer_query got fixed between kernel 6.3.1..13 
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:23 +02:00
David Heidelberg
d3f26cbbe1 Revert "lima/ci: temporarily disable deqp-egl tests due to timeouts" 
This reverts commit be2619766b.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:23 +02:00
David Heidelberg
c467d760cb ci/freedreno: add fails introduced by upreving to 6.3.13 
Some of these fails/crashes was already present when trying 6.3.4,
two disappeared, one new crash appeared. Identical `.config`.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9247

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:23 +02:00
David Heidelberg
bd2b31a89c ci: update kernel to 6.3.13 
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:23 +02:00
David Heidelberg
23158e9a3f ci: build kernel in gfx-ci/linux and just use binaries in Mesa3D CI 
This bring visible speedup while preparing the rootfs and containers.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>
 2023-07-16 02:11:23 +02:00
Alyssa Rosenzweig
9bcdc45ee7 nir: Devendor load_sample_mask 
AGX will use this too for its MSAA lowerings.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24148>
 2023-07-15 19:48:30 +00:00
Alyssa Rosenzweig
56d61d9a64 nir: Add fence_{pbe,mem}_to_tex(_pixel)_agx intrinsics 
Read-after-write hazards require special handling on AGX, since image loads are
implemented with texturing. Add intrinsics to handle these hazards.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24148>
 2023-07-15 19:48:30 +00:00
Faith Ekstrand
259ba104f7 nv50/ir: Support vector movs 
nir_opt_mov and nir_op_vecN are only the same if the mov is only a
single component.  Otherwise the vec loop will try to access src[c]
where c > 0 which breaks for nir_op_mov.  It's uncommon but scalar
back-ends can see vector movs so we need to handle this correctly.

Fixes: 6513c675ad ("nv50/ir/nir: implement nir_alu_instr handling")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24167>
 2023-07-15 15:53:40 +00:00
Semjon Kravtsenko
3982445728 glx: Assign unique serial number to GLXBadFBConfig error 
Fixes: e89e1f5049 ("glx: Fix error handling yet again in CreateContextAttribs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9171
Tested-by: yan12125
Co-authored-by: XRevan86
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23762>
 2023-07-15 03:27:17 +00:00
WinLinux1028
9590bce3e2 radeonsi: prefix function with si_ to prevent name collision 
Fixed a build error caused by multiple gfx11_init_query symbols when building with iris and radeonsi specified in gallium-drivers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9238
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24045>
 2023-07-14 22:37:05 +00:00
Sagar Ghuge
27d30fe3c0 isl: Disable MCS compression just on ACM platform 
We're still seeing failures with render target reads of multisampled
images on Alchemist platforms, but Meteorlake doesn't appear to have
that issue. Enable MCS on Meteorlake.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22802>
 2023-07-14 21:17:19 +00:00
Sagar Ghuge
efa6594536 intel/compiler: Look at 2 register worth of data instead of 4 
Sampler always writes 4/8 register worth of data but for ld_mcs only
valid data is in first two register. So with 16-bit payload, we need to
split 2-32bit registers into 4-16-bit payload.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22802>
 2023-07-14 21:17:19 +00:00
Rohan Garg
8b93fa149b iris: migrate WA 14016118574 to use the WA framework 
Fixes: 58829d9f1 ("iris: implement Wa_14016118574")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156>
 2023-07-14 21:29:28 +02:00
Rohan Garg
83716b08cf iris: migrate WA 14013910100 to use the WA framework 
Fixes: eeb3f4594d ("intel/xehp: Implement XeHP workaround Wa_14013910100.")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156>
 2023-07-14 21:29:27 +02:00
Thong Thai
e85a18a9af Update radeon_vcn_enc.c 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24151>
 2023-07-14 17:46:03 +00:00