Commit Graph

183087 Commits

Author SHA1 Message Date
Karol Herbst
798cb57680 rusticl/kernel: take set kernel arguments into account for CL_KERNEL_LOCAL_MEM_SIZE
Cc: mesa-stable
Reviewed-by @LingMan

(cherry picked from commit 3a9b1baa80)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-08 09:18:50 -08:00
Marek Olšák
f65e49341b glsl: fix corruption due to blake3 hash not being set for nir_opt_undef
NIR is generated sooner, so we need to set it sooner.
This fixes Viewperf13/CATIA_car_04.

Fixes: cbfc225e2b - glsl: switch to a full nir based linker

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit d09ba36f98)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-08 09:18:44 -08:00
José Roberto de Souza
6cb52a8838 anv: Allow larger SLM sizes for task and mesh shader
It was hard-coded to 64k but Xe2 platforms and newer supports
larger SLM sizes.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Cc: mesa-stable
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 7ac9ac0f93)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-08 09:18:44 -08:00
Icenowy Zheng
949faebea4 zink: do not set transform feedback bits when not available
Currently the list of buffer usage bits specified is hardcoded with
transform feedback bits, which leads to a validation layer error report
with ID VUID-VkBufferCreateInfo-None-09499 when EXT_transform_feedback
is not available.

Only set these bits when EXT_transform_feedback extension is really
available to suppress this error.

Cc: mesa-stable
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 70fa598696)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-06 09:40:12 -08:00
David Rosca
bca4ba9866 frontends/va: Get buffer feedback with locked mutex in MapBuffer
Fixes: 93d434362b ("frontends/va: Move encode fence to coded buffer")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12344

Tested-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
(cherry picked from commit 36bedf6c80)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-06 09:40:12 -08:00
Hyunjun Ko
0d5f54b5ca anv: handle negative value of slot index for h265 decoding.
Fixes: 8d519eb5 ("anv: add initial video decode support for h265")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5ecea6ec4a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-06 09:40:11 -08:00
Lionel Landwerlin
e8fdb9fe5c anv: ensure null-rt bit in compiler isn't used when there is ds attachment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15987f49bb ("anv: avoid setting up a null RT unless needed")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12396
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit 98cdb9349a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-06 09:40:10 -08:00
Caio Oliveira
17381f3190 intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+
Fix invalid SWSB annotation in dEQP-VK.glsl.builtin.precision.mix.mediump.vec4 for LNL.

Fixes: 4a24f49b57 ("intel/compiler/xe2: Implement codegen of three-source instructions.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 6968794c50)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-06 09:40:10 -08:00
Karol Herbst
eb83b614c9 rusticl: stop using system headers for CL and GL
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit f75ba4f9e3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
Karol Herbst
32a93c197e rusticl/queue: add a life check to prevent applications dead locking
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit ccfeda77bd)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
Samuel Pitoiset
ded1ec58f7 radv: disable logic op for float/srgb formats
The Vulkan spec says:
    "The application can enable a logical operation between the
     fragment’s color values and the existing value in the framebuffer
     attachment. This logical operation is applied prior to updating
     the framebuffer attachment. Logical operations are applied only
     for signed and unsigned integer and normalized integer
     framebuffers. Logical operations are not applied to floating-point
     or sRGB format color attachments."

Missing VKCTS coverage has been reported.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12345
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 03b037a0e3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
Samuel Pitoiset
2f364fa240 radv: fix adding the BO to cmdbuf list when emitting buffer markers
Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 370e392313)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
David Rosca
fa57ff1528 radv: Fix sampling from image layers of video decode target
Video decode target needs custom height alignment, but tex descriptor
still needs to be set to the original size the image was created with.
This makes the descriptor wrong for layer > 0, so we need to calculate
the layer offset and add it to bo address for this case.

Fixes: 5deb476095 ("radv: align video images internal width/height inside the driver.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3474978d52)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
David Rosca
0a00c8471f radv/video: Use correct array index for decode target and DPB images
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12057
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ca0cb78869)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
David Rosca
e90c776fa0 radv/video: Fix DPB tier2 surface params
Fixes: 3e2c768aa8 ("radv/vcn: enable dynamic dpb tier 2 for h264/h265 on navi21+")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8dabb480e2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:28 -08:00
Qiang Yu
4c49b19a8c radeonsi: fix unigine heaven crash when use aco on gfx8/9
Unigine Heaven crash on GFX8/9 when use aco:
  heaven_x64: ../../amd/mesa/src/gallium/drivers/radeonsi/si_nir_lower_abi.c:813: lower_tex: Assertion `samp_index >= 0 && comp_index >= 0' failed.

GFX8/9 will clamp texture comparison value in si_nir_lower_abi,
but it has to be done after si_nir_lower_resource.

Fixes: ae933169 ("radeonsi: lower NIR resource srcs to descriptors last")
(cherry picked from commit 8609f49d05)

Conflicts:
        src/gallium/drivers/radeonsi/si_shader.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
2025-01-03 11:38:27 -08:00
Rob Clark
467783980a freedreno/a6xx: Align lrz height to 32
Emperically this seems to be required when doing a linear clear of the
tiled LRZ buffer (because height needs to match aligned height for a
linear clear to dtrt).

Issue could be reproduced with nolrzfc and:

  glmark2 -s 1472x920 --visual-config samples=2 -b terrain

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12336
Fixes: a127a78548 ("freedreno: Re-enable LRZ for a7xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
(cherry picked from commit 3759889846)

Conflicts:
	src/gallium/drivers/freedreno/a6xx/fd6_resource.cc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 16:16:01 -08:00
Thomas H.P. Andersen
c4aa2be477 drirc/nvk: force_vk_vendor=-1 for Artifact Classic
Without this the game crashes during the loading screen.

The game uses vkUpdateDescriptorSetWithTemplate and, in certain cases,
passes VkDescriptorBufferInfo structures where the offset + range
exceeds the size of the buffer. This triggers an assertion when
vk_buffer_range() is called, causing the game to crash.

When the nvidia vendor id is used the range is consistently set to 65536.
Without it the range varies and is much smaller - never exceeding 1000.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12349
Cc: stable
Reviewed-by: Faith Ekstrand <None>
(cherry picked from commit e38150f2fa)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 16:13:23 -08:00
Georg Lehmann
cd01162e81 aco/insert_exec: reset top exec for p_discard_if
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12363
Fixes: 31f62a6123 ("aco/insert_exec: don't always reset top exec")
(cherry picked from commit 272ff275fa)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 16:08:27 -08:00
Boris Brezillon
d72bf5b122 pan/cs: Fix cs_builder allocation failure robustness
There's more than one error-path out of cs_alloc_ins_block(), but only
one of them got the discar_instr_slot treatment. Instead of plugging
this in one more time, let's move this handling up to cs_alloc_ins(),
where we can easily whack two birds with one stone. This makes us
consistently return NULL on error here.

At the same time, we need to patch up cs_flush_block_instrs() here,
because we don't actually set the buffer invalid here. So let's
check for NULL here instead, which is the new contract.

Fixes: 0e6aaab00a ("pan/cs: add block to handle registers backup in exception handler")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
(cherry picked from commit 3006c2a7b6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 16:08:27 -08:00
Peyton Lee
e4276eca9b radeonsi/vpe: add destroy_fence function
implement destroy_fence() for better fence control

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Cc: mesa-stable
(cherry picked from commit ad0dbea49d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 16:08:27 -08:00
Juan A. Suarez Romero
1b706b4c90 v3dv: fix BO allocation
`cleared_and_retried` variable is not required, as once the cache is
empty, in the second retry it will retry it is already empty so it won't
retry a new allocation.

Fixes: 2adea940f1 ("v3dv/bo: adding a BO cache")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit f6766ccadb)

Conflicts:
	src/broadcom/vulkan/v3dv_bo.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 09:55:13 -08:00
Benjamin Lee
e3a186a3ce panvk/csf: fix alpha-to-coverage
The equivalent bit is set correctly on JM, but was missed for CSF. There
shouldn't need to be any shader changes, the alpha-to-coverage flag in
FAU_ATEST_PARAM is set automatically from the bit in DcdFlags0.

Fixes dEQP-VK.pipeline.*.multisample.alpha_to_coverage*

Fixes: 447075eeee ("panfrost: Add support for the CSF job frontend")
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
(cherry picked from commit 3f90d8dfd2)

Conflicts:
	src/panfrost/ci/panfrost-g610-fails.txt
	src/panfrost/vulkan/csf/panvk_vX_cmd_draw.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:31:44 -08:00
Connor Abbott
361316b1ea freedreno/fdl: Fix 3d mipmapping height alignment
We can get into a situation where the layer size for a given mip isn't
large enough to hold the pitch times the aligned height, i.e. the height
isn't aligned. This can happen even if the size is 4K aligned. The
hardware seems not to align the height for us, so we have to use the
MINLAYERSZ hammer.

This was found with a Vulkan test when enabling tiling for mutable
textures on a750, but it's also reproducable via
"bin/texelFetch fs sampler3D 76x76" using piglit.

Cc: mesa-stable
(cherry picked from commit ef4c752b6e)

Conflicts:
	src/freedreno/fdl/fd6_layout_test.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:29:00 -08:00
Janne Grunau
6e0fce2a6e panvk: Silence warning on incompatible DRM render devices
This message is printed on non-panfrost/panthor systems on every
physical device enumeration when panvk is present like in distribution
mesa builds.
This "breaks" gtk-4 tests in the default configuration since they fail
on warning log messages. gtk-4 still forwards the vulkan debug report as
warning messages after fixes for issue 11451 to stop handling it as
critical message.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: d970fe2e9d ("panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11451
(cherry picked from commit b06b62bb13)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:39 -08:00
David Rosca
f63534c991 radeonsi/vcn: Change required FW version for rc_per_pic_ex on VCN3
It only works correctly on 29 and newer.
Also change the old FW message to one time warning.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12353
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
(cherry picked from commit 2f76bdf35d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:38 -08:00
Georg Lehmann
789abcc23e aco/optimizer: fix signed extract of sub dword temps with SDWA
If an instruction didn't already use SDWA convert_to_SDWA in apply_extract
will add ubyte0/uword0 selections for v1b/v2b operands. This loses information
that the instruction doesn't care about the high bits and makes the next
apply_extract_twice fail.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Fixes: 6cb9d39bc2 ("aco: combine extracts with sub-dword definitions")
(cherry picked from commit 3da2d96bc5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:37 -08:00
Samuel Pitoiset
f688dfe665 radv: fix destroying DGC pipelines
They weren't destroyed at all.

Fixes: 9f8684359f ("radv: implement VK_EXT_device_generated_commands")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 58c5766199)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:36 -08:00
Pavel Ondračka
2cbe3468a3 r300: disable microtiling for scanout buffers
Does not work with R300/R400 due to kernel driver limitations.
Suggested by Marek Olšák.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12010
Fixes: f424ef1801
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
(cherry picked from commit 8bc271e90d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:33 -08:00
Lionel Landwerlin
7bea0dd536 anv: fix index buffer size changes
With vkCmdBindIndexBuffer2KHR only the provided size can change which
currently fails to reprogram the index buffer properly.

Signed-off-by: Lionel Landwerlin <llandwerlin@gmail.com>
Fixes: 5c2aca456e ("anv: implement vkCmdBindIndexBuffer2KHR")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12376
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 5e4aeb3ad7)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:32 -08:00
Qiang Yu
cc58288510 aco: fix voffset missing when buffer store base >=4096
Regression on test:
  dEQP-GLES31.functional.geometry_shading.basic.output_256

voffset is missing if buffer store base >=4096, we need to
re-calculate offen after resolve_excess_vmem_const_offset().

Fixes: cdaf269924 ("aco: inline store_vmem_mubuf/emit_single_mubuf_store")
(cherry picked from commit dff14d102d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:29 -08:00
Rohan Garg
29c400ca56 isl: disable aux when creating uncompressed TileY/Tile64 surfaces from compressed ones
Fixes: 8e96b51 ('intel/isl: Assert alignments of surface addresses')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <None>
(cherry picked from commit f96b2c002d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:22 -08:00
Mary Guillemard
c1ecf08e0d nak: Fix 8-bit selection for vectors
This fix at least permutation issues on vec16 of 8-bits values for
cooperative matrix.

Fixes: 9e84e9e44b ("nak: Add base support for 8 and 16-bit types")
Suggested-by: M Henning <drawoc@darkrefraction.com>
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
(cherry picked from commit 979dfaf0bb)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:22 -08:00
David Rosca
6d33b742b0 frontends/va: Don't allow Render/EndPicture without BeginPicture
It's not valid to call RenderPicture and EndPicture without calling
BeginPicture or when BeginPicture fails. FFmpeg will however call
EndPicture when BeginPicture fails, so we need to handle this.
Use target_id, which is assigned in BeginPicture, as an indication
whether we are inside the Begin - End picture sequence.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
(cherry picked from commit 42e765d48b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:21 -08:00
David Rosca
e716ff323b frontends/va: Fix decoding VC1 interlaced video
VC1 has different start code for FRAME and FIELD, so we need to use
FIELD start code for second field.
Also simplify start code search to only look for 00 00 01.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2347
Cc: mesa-stable
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
(cherry picked from commit 6e911cf252)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2025-01-02 08:20:20 -08:00
Mel Henning
5426f640f1 gallium/winsys/nouveau: Don't mark the api PUBLIC
We don't want to export this symbol from our shared object - any use of
this function from outside of mesa (like the ddx) should get the version
from libdrm, not the private copy in mesa.

Fixes: 821f4c8d99 ("nouveau: import libdrm_nouveau")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
(cherry picked from commit 6f6072448d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2024-12-20 18:51:01 -08:00
Job Noorman
0427d36334 ir3,freedreno: remove binning outputs after vs ucp lowering
nir_lower_clip_vs relies on VARYING_SLOT_CLIP_VERTEX which gets removed
when removing the outputs that are unused by the binning vs. Fix this by
only removing the outputs after running nir_lower_clip_vs.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12328
Fixes: 24b422dc3e ("ir3: remove unused outputs for binning pass in NIR")
(cherry picked from commit 419879ee62)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32852>
2024-12-20 18:51:00 -08:00
Jordan Justen
bb5927c31f iris: Check that mem_fence_bo was created
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 8e8097245f ("iris: Emit STATE_SYSTEM_MEM_FENCE_ADDRESS")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit adfd7486c2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
Simon Ser
9a32249031 egl/wayland: fallback to implicit modifiers if advertised by compositor
The Wayland protocol defines INVALID as a special marker indicating
that implicit modifiers are supported. If the driver doesn't support
explicit modifiers and the compositor advertises support for implicit
modifiers, fallback to these.

This effectively restores logic removed in 4c06515892, but only
for the specific case of Wayland instead of affecting all APIs.
(Wayland is one of the few APIs defining a special meaning for
INVALID.)

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 4c06515892 ("dri: revert INVALID modifier special-casing")
(cherry picked from commit da555982b3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
Simon Ser
5457b5af74 egl/wayland: only supply LINEAR modifier when supported
If we supply modifiers to dri_create_image_with_modifiers() and
the driver doesn't support them, the function will fail. We pass
__DRI_IMAGE_USE_LINEAR anyways so stripping the modifier is fine.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 4c06515892 ("dri: revert INVALID modifier special-casing")
(cherry picked from commit d795b4712c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
Simon Ser
0d97c42d7d dri: don't fetch X11 modifiers if we don't support them
If we supply modifiers to dri_create_image_with_modifiers() and
the driver doesn't support them, the function will fail. The X11
server always supports implicit modifiers so we can always fall
back to that.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 4c06515892 ("dri: revert INVALID modifier special-casing")
(cherry picked from commit 655ac4fff6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
David Rosca
18f5161fe9 radeonsi/uvd: Align bitstream buffer to 128 when resizing
Also use the same initial size as VCN.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
(cherry picked from commit cdf2106609)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
David Rosca
cfff580b02 radeonsi/vcn: Align bitstream buffer to 128 when resizing
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2824
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
(cherry picked from commit f1235d13bd)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
Louis-Francis Ratté-Boulianne
7ca563d522 panfrost: Re-emit texture descriptor if the data size has changed
When updating an AFBC-packed resource, the size of the resulting
texture data can change while the BO and modifier stay the same. We
still need to update the texture descriptor in that situation so
that the size is properly reported. Having a smaller size than the
real one might cause artifacts as the GPU doesn't want to read past
the reported size.

A future (more foolproof) fix might involve having a hash key to
track the size of all slices independently, but this patch still
improves the situation and make sure we don't hit a relatively
common issue when using `PAN_MESA_DEBUG=forcepack`.

Fixes: bc55d150a9 ("panfrost: Add support for AFBC packing")
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 30825140d0)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
José Roberto de Souza
99a3dbef34 iris: Emit STATE_SYSTEM_MEM_FENCE_ADDRESS
According to HAS it is necessary to emit this instruction once per
context so MI_MEM_FENCE works properly.

Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 8e8097245f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
José Roberto de Souza
9d2ec701d9 anv: Emit STATE_SYSTEM_MEM_FENCE_ADDRESS
According to HAS it is necessary to emit this instruction once per
context so MI_MEM_FENCE works properly.

Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 2bd3df75e5)

Conflicts:
	src/intel/vulkan/anv_device.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-19 09:52:39 -08:00
Samuel Pitoiset
32a267518c radv: add radv_lower_terminate_to_discard and enable for Indiana Jones
To workaround game bug.

This fixes the rendering issue with eyes.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit c7a7f0244f)

Conflicts:
	src/amd/vulkan/radv_shader.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-18 12:05:42 -08:00
M Henning
e806d032e1 nvk: Fix uninitialized var warnings in host_copy
Fixes: 6c5420cd30 ("nvk: Add host copy functions")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
(cherry picked from commit 5a65300439)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-18 11:28:23 -08:00
José Roberto de Souza
d96ad7736d anv: Always create anv_async_submit in init_copy_video_queue_state()
A next patch will emit more instructions in video and copy queues
for Gfx 200 and newer but the current code only creates anv_async_submit
if device has aux_map.
Instead we can always create anv_async_submit and only submit it to
hardware if any instruction was emited.

Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit b8f93bfd38)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-18 11:28:17 -08:00
José Roberto de Souza
9ba56c1592 intel/genxml/xe2: Add STATE_SYSTEM_MEM_FENCE_ADDRESS instruction
Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit edb33b47ab)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
2024-12-18 11:28:17 -08:00