Commit Graph

56547 Commits

Author SHA1 Message Date
Eric Anholt
77a405dba7 mesa: Make Mesa core set up wrapped texture renderbuffer state.
Everyone was doing effectively the same thing, except for some funky code
reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of
using the texture's _BaseFormat.  swrast's sRGB handling is left in place,
though it should be done by using _mesa_get_render_format() at render time
instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 14:34:14 -07:00
Eric Anholt
5b190d19d3 intel: Simplify renderbuffer-for-texture width setup.
We're looking for the logical width of our level, which is what
image->Width2/Height2 is.  The previous code relied on MSAA textures being
only level 0.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 14:33:43 -07:00
Eric Anholt
749a92786d mesa: Make core Mesa allocate the texture renderbuffer wrapper.
Every driver did the same thing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 14:33:38 -07:00
Eric Anholt
5b9609f59a i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().
Now that depth resolves are handled there, we don't need to make the
temporary renderbuffer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 14:33:33 -07:00
Eric Anholt
40956c5519 i965: Move blorp resolve setup into brw_blorp_blit_miptrees().
There was some comment about trying to avoid marking resolves in
updownsample, but if the downsample is never actually rendered to, then
the required resolve tracked in the downsample will never be executed, so
who cares?

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 14:33:27 -07:00
Tom Stellard
730c90a70e gallivm: Fix build for LLVM < 3.3
The C API versions of the LLVM multithreaded functions were added in
LLVM 3.3.
2013-05-06 11:17:03 -07:00
Tom Stellard
bb94d4d8fe r600g/llvm: Parse config values in register / value pairs
Rather than relying on a predetermined order for the config values.
2013-05-06 10:54:52 -07:00
Tom Stellard
df27320560 r600g/llvm: Don't feed LLVM output through r600_bytecode_build()
The LLVM backend emits raw ISA now, so we can just its output
unmodified.
2013-05-06 10:54:52 -07:00
Tom Stellard
e917ed96ae r600g/llvm: Don't emit CALL_FS for vertex shaders
The LLVM backend takes care of this now.
2013-05-06 10:54:52 -07:00
Matt Turner
1d09a8c3cd i965: Lower bitfieldInsert.
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
    bitfieldExtract at all) since three-source instructions are now
    usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
    it doesn't produce any instructions to be lowered (the other two
    lowering passes that were in a previous iteration of this series
    emitted subtractions which needed to be lowered).

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-05-06 10:17:14 -07:00
Matt Turner
acd2bccd85 i965/vs: Add support for bit instructions.
v2: Rebase on LRP addition.
    Use fix_3src_operand() when emitting BFE and BFI2.
    Add BFE and BFI2 to is_3src_inst check in
      brw_vec4_copy_propagation.cpp.
    Subtract result of FBH from 31 (unless an error) to convert
      MSB counts to LSB counts

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:14 -07:00
Matt Turner
1f0f26d60c i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.

v2: Subtract result of FBH from 31 (unless an error) to convert
    MSB counts to LSB counts.
v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref
    channel_expressions) from appearing multiple times in the IR.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-05-06 10:17:14 -07:00
Matt Turner
fa958182b7 i965: Add support for emitting and disassembling bit instructions.
Specifically
   bfe - for bitfieldExtract()
   bfi1 and bfi2 - for bitfieldInsert()
   bfrev - for bitfieldReverse()
   cbit - for bitCount()
   fbh - for findMSB()
   fbl - for findLSB()

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:14 -07:00
Matt Turner
c71bee757b i965: Print the correct dst and shared-src types for 3-src instructions.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:14 -07:00
Matt Turner
526ffdfc03 i965/gen7: Set src/dst types for 3-src instructions.
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.

v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
    Assert that src2.type (instead of src0.type) matches dest.type since
    it's the primary argument and src0 and src1 might correctly have
    different types.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-05-06 10:17:13 -07:00
Matt Turner
2305047823 i965: Add 3-src destination and shared-source type macros.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:13 -07:00
Matt Turner
4049d48e02 i965: Add Gen7+ fields to brw_instruction and add comments.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:13 -07:00
Matt Turner
dafd050883 glsl: Add a pass to lower bitfield-insert into bfm+bfi.
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.

v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
    Remove spurious temporary assignment and dereference.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:13 -07:00
Matt Turner
9c04b8c28c glsl: Add constant evaluation of bit built-ins.
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type ==
    op[1]->type assertion in ir_constant_expression.cpp.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-05-06 10:17:13 -07:00
Matt Turner
499d8c6545 glsl: Add support for new bit built-ins in ARB_gpu_shader5.
v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:13 -07:00
Matt Turner
44d3287ecd glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:13 -07:00
Matt Turner
f9e37879eb glsl: Rework ir_reader to handle expressions with four operands.
Needed to support the bitfieldInsert() built-in added by
ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:12 -07:00
Matt Turner
f99f78e49a mesa: Add infrastructure for ARB_gpu_shader5.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-05-06 10:17:12 -07:00
Tom Stellard
914d797797 radeon/llvm: Always build libradeonllvm as static
This library is very small, so there is not much to gain from building
it as a shared library.  Also, when linking statically with LLVM, a
shared libradeonllvm exports LLVM symbols and creates problems when
used with other shared objects that also link statically to LLVM.

Reviewed-by: Mathias.Froehlich@web.de
2013-05-06 09:06:10 -07:00
Tom Stellard
024fe6852a radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2
The LLVM C API is considered stable and should never change, so it
is much more desirable to use than the LLVM C++ API, which is constantly in
flux.

v2:
  - Split target initialization and lookup into separate functions

Reviewed-by: Mathias.Froehlich@web.de
2013-05-06 09:06:06 -07:00
Tom Stellard
55eb8eaaa8 gallivm: Move LLVMStartMultithreaded() static initializer into gallivm
This does not solve all of the problems with using LLVM in a
multithreaded enivronment, but it should help in some cases.

Reviewed-by: Mathias.Froehlich@web.de
2013-05-06 09:06:03 -07:00
Tom Stellard
7cc98ea88f radeon/llvm: Don't use the global context when parsing LLVM IR
This leads to crashes when multiple threads try to compile compute
shaders in the same time.

Fixes a crash in bfgminer when using more than one thread.
2013-05-06 09:06:00 -07:00
Eric Anholt
bd850cb4f2 i965: Remove GL_ARB_color_buffer_float from GL core contexts.
Of the 3 controls in the extension, one was kept in GL core and the other
two were explicitly deprecated and the reasonable default behavior was
encoded in the spec.  By not exposing the extension, we avoid shader
recompiles when switching between float and unorm color buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-06 09:01:51 -07:00
Tom Stellard
ec143dc0b1 r600g/llvm: Update radeon family mappings for LLVM backend
New processors were added to the backend to distinguish between
GPUs with and without vertex caches.
2013-05-06 08:22:24 -07:00
Chia-I Wu
5cca6b6280 android: libsync is needed on Android 4.2+ for any driver
Add libsync not only for MESA_BUILD_CLASSIC, but also for MESA_BUILD_GALLIUM.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-05-06 07:20:08 -07:00
Chia-I Wu
da109d56d5 android: add ilo to the build system
It can be selected with

  BOARD_GPU_DRIVERS := ilo

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2013-05-06 07:20:07 -07:00
Eric Anholt
739b88330c glsl: Flip around "if" statements with empty "then" blocks.
This cleans up some funny-looking code in some unigine shaders I was
looking at.  Also slightly helps on planeshift and a few shaders in an
upcoming Valve release.

total instructions in shared programs: 1653715 -> 1653587 (-0.01%)
instructions in affected programs:     16550 -> 16422 (-0.77%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-05 13:20:42 -07:00
Chia-I Wu
008346273c ilo: correctly set return types of sampler messages
Correctly set the types of the temporaries.  We do not want type conversions
when moving the results to the final destinations.
2013-05-05 14:36:39 +08:00
Vincent Lejeune
b42fe195a2 r600g/llvm: Undefines unrequired texture coord values
This is a port of "r600g:mask unused source components for SAMPLE"
patch from Vadim Girlin.
2013-05-04 23:38:50 +02:00
Maarten Lankhorst
c4150123aa nvc0: fixup video decoding with 2D_ARRAY
Signed-off-by: Maarten Lankhorst <m.b.lankhorst@gmail.com>
2013-05-04 20:56:23 +02:00
Chia-I Wu
8c347d4e57 gallium: fix type of flags in pipe_context::flush()
It should be unsigned, not enum pipe_flush_flags.

Fixed a build error:

  src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error:
  invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive]

v2: replace all occurrences of enum pipe_flush_flags by unsigned

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>

[olv: document the parameter now that the type is unsigned]
2013-05-04 17:32:10 +08:00
Eric Anholt
cbf3462c35 i965: Enable fast clears on non-8x4-aligned sizes.
Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
The workaround was to avoid bad primitive/surface sizes, but that's worked
around as of a14dc4f92c.  (One might note
that pre-gen7 we don't know that the right half of an 8x4 at the right
edge is actually our pixels, but we're already clobbering those pixels for
depth resolves anyway and more work would be required to avoid that).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-05-03 20:59:51 -07:00
Brian Paul
76084907fb vbo: add comments, const qualifiers
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
0baf32508a mesa: whitespace, formatting fixes, etc in api_arrayelt.c
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
7c9e5afe81 vbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()
As we do for the other commands which can appear between glBegin/End.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
7b762305d5 mesa: change ctx->Driver.NeedFlush to GLbitfield and update comment
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
36c83ccca0 mesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
af30987a69 vbo: update comments for vbo_save_NotifyBegin()
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
4ea05bcba6 vbo: implement primitive merging for glBegin/End sequences
A surprising number of apps and benchmarks have poor code like this:

glBegin(GL_LINE_STRIP);
glVertex(v1);
glVertex(v2);
glEnd();
// Possibly some no-op state changes here
glBegin(GL_LINE_STRIP);
glVertex(v3);
glVertex(v4);
glEnd();
// repeat many, many times.

The above sequence can be converted into:

glBegin(GL_LINES);
glVertex(v1);
glVertex(v2);
glVertex(v3);
glVertex(v4);
glEnd();

Similarly for GL_POINTS, GL_TRIANGLES, etc.

Merging was already implemented for GL_QUADS in the display list code.
Now other prim types are handled and it's also done for immediate mode.

In one case:
                                 before   after
-----------------------------------------------
number of st_draw_vbo() calls:     141      45
number of _mesa_prims issued:     7520     632

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Brian Paul
3702d25082 vbo: create a few utility functions for merging primitives
To be used by following commit.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 19:00:07 -06:00
Zack Rusin
a232afdbfb draw/pt: adjust overflow calculations
gallium lies. buffer_size is not actually buffer_size but available
size, which is 'buffer_size - buffer_offset' so by adding buffer
offset we'd incorrectly compute overflow.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 07:07:33 -04:00
Zack Rusin
8490d21cbe tgsi/ureg: make the dst register match the src indirection
In ureg src registers could have an indirect register that was
either a temp or an addr register, while dst registers allowed
only addr. That made moving between them a little difficult so
make them behave the same way and allow temp's and addr registers
as indirect files for both (tgsi supports it, just ureg didn't).

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-05-03 07:07:33 -04:00
Roland Scheidegger
23025ed15d gallium: tgsi documentation updates and clarification for integer opcodes.
A lot of them were missing. Others were moved from the Compute ISA
to a new Integer ISA section as that seemed more appropriate.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-03 21:36:28 +02:00
Roland Scheidegger
ae507b6260 llvmpipe: get rid of depth swizzling.
Eliminating this we no longer need to copy between linear and swizzled layout.
This is probably not quite ideal since it's a bit more work for now, could do
some optimizations by moving depth testing outside the fragment shader loop
(but tricky for early depth test as we don't have neither the mask nor the
interpolated z in the right order handy).
The large amount of tile/untile code is no longer needed will be deleted
in next commit.
No piglit regressions.
v2: change a forgotten LAYOUT_NONE to LAYOUT_LINEAR.
v3: fix (bogus) uninitialized variable warnings, add comments, fix a bad type

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-03 21:36:20 +02:00
Lauri Kasanen
e495d88453 r600g: Correctly initialize the shader key, v2
Assigning a struct only copies the members - any padding is left as is.

Thus this code:

struct foo_t foo;
foo = bar;

leaves the padding of foo intact, ie uninitialized random garbage.

This patch fixes constant shader recompiles by initializing the struct
to zero. For completeness, memcpy is used to copy the key to the shader
struct.

NOTE: This is a candidate for the stable branches.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-05-03 19:28:57 +02:00