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Author SHA1 Message Date
Iago Toral Quiroga
b95bb44c61 broadcom/compiler: always clamp results from logic ops 
We have also been clamping our integer RTs in GL for a while now.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:41 +00:00
Iago Toral Quiroga
fb80e830ef v3dv: don't set lower_wpos_pntc for Vulkan 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:41 +00:00
Iago Toral Quiroga
87e167baa1 broadcom/compiler: move vulkan's point coord lowering to the driver 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
59018b0228 broadcom/compiler: move uniform offset lowering from compiler to GL driver 
We only need this in GL so move it there.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
f5931ba6d8 broadcom/compiler: use NIR's lowering for dispatch base 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
9211b9afdf broadcom/compiler: stop asserting on Vulkan environment 
The idea is to eventually get rid of key->environment.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
fc0ca7407b v3dv: fix incorrect key setup 
We had this incorrectly included inside the body of loop over
the subpass attachments so when all attachments are unused we
would not set this correctly.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
ebe66479fb nir/lower_robustness: drop skip_ubo_0 option 
v3dv was the only user and it no longer requires this.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Iago Toral Quiroga
e941732ab1 v3dv: stop incrementing UBO indices by one 
This matches what we do for OpenGL, allowing us to
have the same compiler behavior for both worlds.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24396>
 2023-08-03 06:32:40 +00:00
Samuel Pitoiset
c733c166d7 radv: add radv_graphics_shaders_compile() to compile graphics shaders 
Similar to radv_compile_cs() but for all graphics stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
 2023-08-03 06:04:52 +00:00
Samuel Pitoiset
5be4446abe radv: add a struct for the retained shaders and GPL 
This will be used to remove the pipeline dependency completely when
compiling graphics shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
 2023-08-03 06:04:52 +00:00
Samuel Pitoiset
2050f2fe48 radv: inline radv_pipeline_get_nir() in radv_graphics_pipeline_compile() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
 2023-08-03 06:04:52 +00:00
Samuel Pitoiset
581f4701be radv: stop passing a graphics pipeline to radv_pipeline_nir_to_asm() 
Also rename the function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
 2023-08-03 06:04:52 +00:00
Samuel Pitoiset
efbb6de035 radv: remove unnecessary check in radv_pipeline_nir_to_asm() 
If a NIR stage is present, there shouldn't be any compiled binaries
in the same stage slot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24423>
 2023-08-03 06:04:52 +00:00
Jordan Justen
19d0b24927 intel/dev: Support xe2 device init (for intel_device_info_test) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24419>
 2023-08-03 00:10:35 +00:00
Jordan Justen
b80bcd8327 intel/dev: Add LNL platform enum 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24421>
 2023-08-02 23:38:37 +00:00
Dave Airlie
773d77dc7e llvmpipe: fix fragdata/lastfragdata heuristic a bit more. 
This heuristic broke when zmike lowered fragcolor using NIR,

This fixes a regression in:
dEQP-GLES31.functional.shaders.framebuffer_fetch.basic.last_frag_data

Fixes: db1371cce1 ("llvmpipe: fix handling of unused color attachments")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24435>
 2023-08-03 08:51:41 +10:00
Eric Engestrom
17ee184e25 docs: update calendar for 23.1.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24455>
 2023-08-02 20:39:53 +01:00
Eric Engestrom
17b856d97a docs: add sha256sum for 23.1.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24455>
 2023-08-02 20:39:43 +01:00
Eric Engestrom
71a07831a9 docs: add release notes for 23.1.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24455>
 2023-08-02 20:39:29 +01:00
Gert Wollny
4c3fc03d7f r600/sfn: AR loads should depend on all previous non ALU instructions 
These instructions could be re-ordered, so depending just on the last one
is not sufficient.

Fixes: d21054b4bc
   r600/sfn: Add pass to split address and index register loads

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24454>
 2023-08-02 18:55:36 +00:00
Gert Wollny
5b75d86df9 r600/sfn: Only switch to other CF if no AR uses are pending 
Otherwise we end up with an incorrect array load (or an assertion failure).

Fixes: d617052db6
    r600/sfn: take address loads into account when scheduling

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24454>
 2023-08-02 18:55:36 +00:00
Eric Engestrom
b1ce5fe20a ci: drop rule for non-existent src/include/ 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24449>
 2023-08-02 18:20:46 +00:00
Eric Engestrom
f69e60406f ci: add .core-rules to .gallium-core-rules 
All the users of the latter were already getting the former through
other rules so there's no functional change, but it's more correct.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24449>
 2023-08-02 18:20:46 +00:00
Samuel Pitoiset
e7cf235422 radv: add support for emitting TCS epilogs in cmdbuf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:19 +00:00
Samuel Pitoiset
ce05412417 radv: add support for a TCS epilogs cache in the device 
Similar to VS prologs and PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:19 +00:00
Samuel Pitoiset
8abf8dad6b radv: add infra for creating TCS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
198291f45b radv: add radv_tcs_epilog_key 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
f950eae10f radv: declare new argument for the TCS epilog PC 
To jump to the TCS epilog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
c12ab8af96 radv: track if TES reads tess factors differently 
This information will be passed through the TCS epilog key.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
61999253de radv: do not write tess factors in main TCS when it has an epilog 
Tess factors will be written by TCS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
54a6eb6613 radv: assume a TCS needs an epilog unless it's linked with a TES 
For shader object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Samuel Pitoiset
f4ec2e7bb3 radv,aco: move has_epilog to radv_shader_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
 2023-08-02 16:59:18 +00:00
Eric Engestrom
eadc72d9de broadcom/ci: reduce v3dv-rpi4-vk timeout to 30min (instead of 1h) 
This means that when things go wrong, we don't hold the runner (and Marge)
for as long, while still having a 2x margin over the usual run time.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24402>
 2023-08-02 16:36:51 +00:00
Eric Engestrom
4346fe8e2a broadcom/ci: reduce v3d-rpi4-traces timeout to 30min (instead of 1h) 
This means that when things go wrong, we don't hold the runner (and Marge)
for as long, while still having a 2x margin over the usual run time.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24402>
 2023-08-02 16:36:50 +00:00
Eric Engestrom
9ca031b4a8 broadcom/ci: reduce v3d-rpi4-gl timeout to 30min (instead of 1h) 
This means that when things go wrong, we don't hold the runner (and Marge)
for as long, while still having a 2x margin over the usual run time.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24402>
 2023-08-02 16:36:50 +00:00
Eric Engestrom
b23d4d86dd broadcom/ci: reduce vc4-rpi3-gl timeout to 30min (instead of 1h) 
This means that when things go wrong, we don't hold the runner (and Marge)
for as long, while still having a 2x margin over the usual run time.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24402>
 2023-08-02 16:36:50 +00:00
Alyssa Rosenzweig
9ee4de829e nir: Remove register load/store builders 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24450>
 2023-08-02 10:27:17 -04:00
Alyssa Rosenzweig
17d66055ae nir: Remove reg_intrinsics parameter to convert_from_ssa 
All users must set it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24450>
 2023-08-02 10:26:45 -04:00
Alyssa Rosenzweig
11a161b9b9 nir: Remove lower_vec_to_movs 
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24450>
 2023-08-02 10:26:45 -04:00
Alyssa Rosenzweig
f218a2c3df nir: Remove lower_to_source_mods 
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24450>
 2023-08-02 10:26:45 -04:00
Eric Engestrom
61d24ea88c ci: reduce bare-metal retries of poe_run to only 3 attempts 
10 is overkill, if we fail that many times in a row we should stop
trying on this runner.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24407>
 2023-08-02 11:23:44 +00:00
Eric Engestrom
52ee1f6fa6 ci: add a 10min job timeout to formatting checks 
They both take only a few seconds, but it can take up to a minute for
setting up the job, and various external factors such as network can add
delays, so let's round it up to a generous 10 minutes.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24431>
 2023-08-02 10:28:07 +00:00
David Heidelberg
39ddc509e1 ci/freedreno: document another mapbuffer flake on a530 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24441>
 2023-08-02 08:48:20 +00:00
Juan A. Suarez Romero
08579810d1 broadcom/ci: update expected results 
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24437>
 2023-08-02 08:16:20 +00:00
Samuel Pitoiset
f433d39935 aco: add infra for compiling TCS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24417>
 2023-08-02 07:29:50 +00:00
Qiang Yu
572625ea6c aco: extract aco_compile_shader_part from aco_compile_ps_epilog 
Will be shared with radeonsi tcs epilog and other shader parts build.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24417>
 2023-08-02 07:29:50 +00:00
Samuel Pitoiset
ac99fbe591 aco: add aco_shader_info::tcs::has_epilog 
This will be used by both RADV and RadeonSI to jump from the main TCS
to the epilog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24417>
 2023-08-02 07:29:50 +00:00
Samuel Pitoiset
ac40924a3b radv: allow to use fixed IO locations for VS<->TCS<->TES without linking 
For shader objects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24408>
 2023-08-02 06:54:09 +00:00
Samuel Pitoiset
ec1e11ab23 amd,radeonsi: move si_shader_io_get_unique_index_patch() to common code 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24408>
 2023-08-02 06:54:09 +00:00