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Author SHA1 Message Date
Jason Ekstrand
75755e0eba turnip: Pretend to support Vulkan 1.2 
It doesn't really support any Vulkan properly yet so why not claim 1.2?
This was an easier way of fixing the build than trying to roll it
forward to a later version of ANV's entrypoint generator scripts.
 2020-01-15 08:34:57 -06:00
Jason Ekstrand
ac0c7ad2c2 vulkan: Update the XML and headers to 1.2.131 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2020-01-15 08:07:04 -06:00
Michel Dänzer
8775b742ea gitlab-ci: Stop using manual jobs for merge requests 
They were causing trouble with Marge Bot: The project settings require
that the pipeline succeeds before a merge request (MR) can be merged,
otherwise Marge doesn't wait for the pipeline to succeed before merging
an MR assigned to her. But Marge can't start manual jobs, so she would
always time out waiting for pipelines with manual jobs.

To avoid this, use these rules:
* Run the pipeline by default for MRs and main project branches changing
  any files affecting it.
* For other MRs, run a single dummy job which always succeeds.
* Don't run any jobs for main project branch changes (e.g. from an MR
  having been merged) not affecting the pipeline.
* Allow jobs to be started manually on branches of forked projects, as
  before.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>
 2020-01-15 10:31:01 +00:00
Pierre-Eric Pelloux-Prayer
7b0b085c94 radeonsi: drop the negation from fmask_is_not_identity 
This change eases code reading ("fmask_is_identity = true" is clearer than
"fmask_is_not_identity = false").
Initialization is not changed so fmask_is_identity is false when a texture is
created.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
 2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
3a527eda7c radeonsi: unbind image before compute clear 
It's not used and avoid infinite recursion when used from si_compute_expand_fmask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
 2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
c2df5389bb radeonsi: make sure fmask expand is done if needed 
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2248
Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
 2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
b5e748b49b radeonsi: fix fmask expand compute shader 
'coord' variable was using TGSI_WRITEMASK_XYZ so subsequent uses of
TGSI_WRITEMASK_W were dropped.
The result for a 2 samples program was:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  2: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  3: END

instead of the expected:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: MOV TEMP[0].w, IMM[0].yyyy
  2: LOAD TEMP[1], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  3: MOV TEMP[0].w, IMM[0].zzzz
  4: LOAD TEMP[2], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  5: MOV TEMP[0].w, IMM[0].yyyy
  6: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  7: MOV TEMP[0].w, IMM[0].zzzz
  8: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  9: END

This fixes half of https://gitlab.freedesktop.org/mesa/mesa/issues/2248

Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
 2020-01-15 10:10:15 +00:00
Nataraj Deshpande
be08e6a449 egl/android: Restrict minimum triple buffering for android color_buffers 
The patch restricts triple buffering as minimum at driver for android
color_buffers in order to fix onscreen performance hit for T-Rex and
Manhattan.

v2: Update min_buffer check condition (Tapani Pälli)
v3: further code cleanup (Eric Engestrom)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2332
Fixes: 0661c357c6 ("egl/android: Update color_buffers querying for buffer age")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>
 2020-01-15 09:42:08 +00:00
Lionel Landwerlin
a014105498 anv: fix pipeline switch back for non pipelined states 
Setting state base address can happen even before pipeline is
selected. Also we must ensure it is set to 3D for Gen12, we can't
switch back to an invalid pipeline value (UINT32_MAX).

v2: Reuse helpers (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b34422db5e ("anv: Implement Gen12 workaround for non pipelined state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
 2020-01-15 11:14:43 +02:00
Samuel Pitoiset
fce28a7341 radv/gfx10: simplify some duplicated NGG GS code 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
 2020-01-15 07:45:29 +00:00
Samuel Pitoiset
53b50be35c radv/gfx10: enable all CUs if NGG is never used 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
 2020-01-15 07:45:29 +00:00
Samuel Pitoiset
5ff12322c9 radv: only use VkSamplerCreateInfo::compareOp if enabled 
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
 2020-01-15 08:16:15 +01:00
Iago Toral Quiroga
3f3ec07be5 v3d: fix bug when checking result of syncobj fence import 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
 2020-01-15 07:53:58 +01:00
Jonathan Marek
222e127e39 st/mesa: run st_nir_lower_tex_src_plane for lowered xyuv/ayuv 
Has the effect of removing the nir_tex_src_plane for these formats too.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
 2020-01-15 02:20:00 +00:00
Jonathan Marek
a554b45d73 st/mesa: don't lower YUV when driver supports it natively 
This fixes YUYV support on etnaviv.

Fixes: 7404833c "gallium: add handling for YUV planar surfaces"

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
 2020-01-15 02:20:00 +00:00
Bas Nieuwenhuizen
4e3c81517b radv: Disable VK_EXT_sample_locations on GFX10. 
Workaround for https://gitlab.freedesktop.org/mesa/mesa/issues/2163

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
 2020-01-15 01:54:27 +00:00
Gurchetan Singh
6c978b1362 st/mesa: implement EGLImageTargetTexStorage 
We can now support this extension.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
 2020-01-15 01:18:54 +00:00
Gurchetan Singh
2f1032f8f2 st/mesa: refactor egl image binding a bit 
We'll need it for egl image tex storage.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
 2020-01-15 01:18:54 +00:00
Gurchetan Singh
be347863ba st/dri: track if image is created by a dmabuf 
Will be used by EXT_EGL_image_storage later.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
 2020-01-15 01:18:54 +00:00
Rob Clark
2629cb627c freedreno/ir3: rename instructions 
Turns out this range of opcodes are more general purpose if/else/endif
instructions.

We should re-work tess to create a basic block and use normal flow
control.  And possibly (for a6xx+) optimize cases to use if/else/endif
when appropriate.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
 2020-01-15 00:56:24 +00:00
Elie Tournier
22c5c54a4f nir/algebraic: sqrt(x)*sqrt(x) -> fabs(x) 
total instructions in shared programs: 12840840 -> 12839341 (-0.01%)
instructions in affected programs: 122581 -> 121082 (-1.22%)
helped: 559
HURT: 0

total cycles in shared programs: 302505756 -> 302490031 (<.01%)
cycles in affected programs: 2022900 -> 2007175 (-0.78%)
helped: 1090
HURT: 130

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
 2020-01-15 00:30:52 +00:00
Elie Tournier
6f394343b1 nir/algebraic: i2f(f2i()) -> trunc() 
total instructions in shared programs: 12840968 -> 12840784 (<.01%)
instructions in affected programs: 17886 -> 17702 (-1.03%)
helped: 77
HURT: 0

total cycles in shared programs: 302508917 -> 302505592 (<.01%)
cycles in affected programs: 249964 -> 246639 (-1.33%)
helped: 70
HURT: 7

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
 2020-01-15 00:30:52 +00:00
Eric Anholt
3d9a3d0be0 i965: Reuse the new core glsl_count_dword_slots(). 
The only difference I could see was treating interfaces like structs.
Maintain that case.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
 2020-01-14 23:55:00 +00:00
Eric Anholt
bc4f089d01 mesa/st: Move the dword slot counting function to glsl_types as well. 
To implement NIR-to-TGSI, we need to be able to get the size of the
uniform variable for the TGSI declaration, not just the
.driver_location.  With its location in mesa/st, drivers couldn't link
to it from nir-to-tgsi.

This feels like a common enough function to want, so let's share it in
the core compiler.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
 2020-01-14 23:55:00 +00:00
Eric Anholt
4cabd4812a mesa/prog: Reuse count_vec4_slots() from ir_to_mesa. 
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
 2020-01-14 23:55:00 +00:00
Eric Anholt
74ee3f76de mesa/st: Move the vec4 type size function into core GLSL types. 
The only bit that gallium varied on was handling of bindless.  We can
retain previous behavior for count_attribute_slots() by passing in
"true" (though I suspect this is just giving a silly answer to a silly
question), and delete our recursive function from mesa/st.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
 2020-01-14 23:55:00 +00:00
Eric Anholt
b807f7a43a mesa/st: Deduplicate the NIR uniform lowering code. 
Just a little refactor as I go looking at the type size functions.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
 2020-01-14 23:55:00 +00:00
Marek Olšák
8832a88434 radeonsi: move PS LLVM code into si_shader_llvm_ps.c 
This is an attempt to clean up si_shader.c.

v2: don't move code that is not specific to LLVM

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
 2020-01-14 18:46:07 -05:00
Marek Olšák
9b60b3ce93 radeonsi: remove always constant ballot_mask_bits from si_llvm_context_init 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
37916a66b1 radeonsi: fold si_create_function into si_llvm_create_func 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
42112010a3 radeonsi: rename si_shader_create -> si_create_shader_variant for clarity 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
63b5d85baa radeonsi: rename si_compile_tgsi_main -> si_build_main_function 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
f4ba457e1e radeonsi: clean up si_shader_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
03950473df radeonsi: merge si_tessctrl_info into si_shader_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
5fa2ab831e radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
18aaceae8d radeonsi: rename si_shader_info -> si_shader_binary_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
7f4a54d5bd radeonsi: remove TGSI from comments 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
b1badf4ad6 radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIR 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Marek Olšák
b144d4be74 radeonsi: don't adjust depth and stencil PS output locations 
this was for compatibility with TGSI

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2020-01-14 18:46:07 -05:00
Caio Marcelo de Oliveira Filho
3cc501be69 nir: Add missing nir_var_mem_global to various passes 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
 2020-01-14 14:42:12 -08:00
Caio Marcelo de Oliveira Filho
d8440a3d2f spirv: Handle PhysicalStorageBuffer in memory barriers 
PhysicalStorageBuffer is lowered to nir_var_mem_global, and
SPIR-V 1.5rev1 in section "3.25. Memory Semantics <id>" says

    UniformMemory

    Apply the memory-ordering constraints to StorageBuffer,
    PhysicalStorageBuffer, or Uniform Storage Class memory.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
 2020-01-14 14:42:12 -08:00
Caio Marcelo de Oliveira Filho
1ec0d4fdff spirv: Drop EXT for PhysicalStorageBuffer symbols 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
 2020-01-14 14:42:12 -08:00
Timur Kristóf
dfaa3c0af6 aco: Flip s_cbranch / s_cselect to optimize out an s_not if possible. 
When possible, get rid of an s_not when all it does is invert the SCC,
and its successor s_cbranch / s_cselect can be inverted instead.

Also modify some parts of instruction_selection to take advantage of
this feature.

Example:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
s2: %3902 = s_cselect_b64 -1, 0, %3900:scc
s2: %407,  s1: %3903:scc = s_not_b64 %3902
s2: %3906,  s1: %3905:scc = s_and_b64 %407, %0:exec
p_cbranch_z %3905:scc
Can now be optimized to:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
p_cbranch_nz %3900:scc

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
 2020-01-14 21:21:06 +01:00
Timur Kristóf
c0f82165a7 aco: Optimize out s_and with exec, when used on uniform bitwise values. 
Previously all booleans needed an s_and with exec when they were turned
into a scalar condition. However, this is not needed for uniform booleans.

v2 by Daniel Schürmann:
- Make the code more readable
v3 by Timur Kristóf:
- Fix regressions, make it work in wave32 mode

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
 2020-01-14 21:21:06 +01:00
Timur Kristóf
1c44129db3 aco: Don't skip combine_instruction when definitions[1] is used. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
 2020-01-14 21:21:06 +01:00
Timur Kristóf
338d03090f aco: Allow optimizing vote_all and nir_op_iand. 
By adding an extra instruction, we can replace the operands of
the s_cselect_b64, which allows it to get picked up by the
optimizer when it looks for uniform booleans.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
 2020-01-14 21:21:06 +01:00
Timur Kristóf
d962bbd895 aco: Implement 64-bit constant propagation. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
 2020-01-14 21:21:06 +01:00
Alyssa Rosenzweig
6bd9c4dc57 panfrost: Fix linear depth textures 
As pointed out by Boris, what we were calling PAN_LINEAR depth textures
was in fact u-interleaved tiled (!), but we never noticed since we
flipped the flag used for sampling, leading to all sorts of fun bugs
when attempting to directly acess depth textures from the CPU. Which
begs the question -- if what we called LINEAR was tiled, how do we
actually render linear depth textures? It turns out the flags for AFBC
form a mali_block_format 2-bit code just like their render-target
counterparts, so we can render to any of the above.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
 2020-01-14 19:42:20 +00:00
Jason Ekstrand
7c16a1ae4e vulkan/wsi: Add a driconf option to force WSI to advertise BGRA8_UNORM first 
The Aztec Ruins benchmark just grabs the first format in the list and
SRGB causes it to render washed out.  With this workaround, it renders
the same as OpenGL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
 2020-01-14 19:27:13 +00:00
Caio Marcelo de Oliveira Filho
edf6a40cb2 intel/fs: Only use SLM fence in compute shaders 
Fixes: b390ff3517 ("intel/fs: Add support for SLM fence in Gen11")
Fixes: e142061399 ("intel/fs: Implement scoped_memory_barrier")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
 2020-01-14 10:55:48 -08:00