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Author SHA1 Message Date
Sviatoslav Peleshko
caa5c23e48 intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line 
At the time this was added to fix some test failures. But it seems that
the failures were happening due to missing cache flushes, so
this extra space is no longer neccessary.

Fixes: 37b4eacc ("intel/isl: Resize clear color buffer to full cacheline")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>
 2023-08-23 12:55:08 +00:00
Georg Lehmann
6d949e18fd aco: fix u2f16 with 32bit input 
The vulkan spec says all conversions are correctly rounded, so if the input
is larger than the largest fp16 value, we need to return MAX_FLOAT/inf
instead of cutting off the msbs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24826>
 2023-08-23 12:25:56 +00:00
Rhys Perry
1d29a1e2fc aco: add adjust_bpermute_dst helper 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>
 2023-08-23 12:36:46 +01:00
Rhys Perry
9169fbf83c aco: clarify bpermute pseudo opcode names 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>
 2023-08-23 12:36:46 +01:00
Rhys Perry
8a024c985f aco: fix p_bpermute_gfx6's exec save/restore with wave32 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>
 2023-08-23 12:36:46 +01:00
Rhys Perry
85957dd6e5 aco: fix p_bpermute_gfx6 with input at non-zero byte 
Same as the other bpermute pseudo instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>
 2023-08-23 12:36:46 +01:00
Chris Spencer
280281f8f7 anv/android: Add support for AHARDWAREBUFFER_FORMAT_YV12 
The default MediaCodec software video decoder returns frames in this
format.

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24388>
 2023-08-23 09:56:03 +00:00
Chris Spencer
35fddccf3f anv/android: Fix importing hardware buffers with planar formats 
Currently, we try to fetch the color aspect of the format and convert that
to an ISL format, which is then used to convert the pixel stride to bytes.
This does not work with planar formats because they don't have a color
aspect, and the planes can be of different sizes anyway, so may not have
the same byte stride. Change to calculate the stride individually for each
plane.

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24388>
 2023-08-23 09:56:03 +00:00
Samuel Pitoiset
203b4054f3 aco: rework printing shader stages 
To avoid printing "unknown" for shader object when eg. VS and TCS
are compiled separately.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24810>
 2023-08-23 09:21:33 +00:00
Feng Jiang
09ff733a3e CODEOWNERS: Add @flynnjiang for VirGL video 
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24570>
 2023-08-23 08:35:08 +00:00
Samuel Pitoiset
aef257fd15 radv: advertise NV_device_generated_commands_compute 
This extension introduces a token for implementing DGC compute, it's
only intended to be used by vkd3d-proton.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Samuel Pitoiset
1a90b7a5da radv: allow DGC on the compute queue 
DGC cmdbuf on ACE are executed as IB1 without chaining because IB2
isn't supported on ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Samuel Pitoiset
559da06755 radv: implement NV_device_generated_commands_compute 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Samuel Pitoiset
a57fe712f7 radv: prepare radv_prepare_dgc() for DGC compute 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Samuel Pitoiset
aa0ca1e1db radv: prepare radv_get_sequence_size() for DGC compute 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Samuel Pitoiset
bb82a3402a radv: track the pipeline bind point for indirect commands layout 
This will be used to implement DGC compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24275>
 2023-08-23 06:05:39 +00:00
Mike Blumenkrantz
fbf3f64c6d zink: sanitize optimal keys 
shader keys represent pipeline states which trigger variants, but not
all shaders are affected by certain states

this adds some sanitizing for the optimal path to ignore shader variants
which won't have any effect for the currently bound shaders, thus reducing
the number of pipelines compiled (both unoptimized and optimized)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>
 2023-08-23 01:39:42 +00:00
Mike Blumenkrantz
dae144aeac zink: use the "set" optimal key for prog last_variant_hash for consistency 
this is the key that has been set during program update for reuse
everywhere else, and everything else in the driver uses it

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>
 2023-08-23 01:39:42 +00:00
Mike Blumenkrantz
d5157356ce zink: don't start multiple cache jobs for the same program 
if there's already a cache job in flight then starting a second one
is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>
 2023-08-23 01:39:42 +00:00
David Rosca
87e2d5d605 frontends/va: Add BT.709 as supported postproc color standard 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>
 2023-08-23 01:01:16 +00:00
David Rosca
33dc69b9fa gallium/auxiliary/vl: Don't set csc matrix in video_buffer/rgb_to_yuv_layer 
It's now handled in va frontend instead.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>
 2023-08-23 01:01:16 +00:00
David Rosca
92690aee95 frontends/va: Set csc matrix in postproc 
Set correct matrix according to format, color standard and range.

Change default value for color range when not explicitly specified.
Use limited range for YUV and full range for RGB.

This also adds support for converting from full range YUV to RGB.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>
 2023-08-23 01:01:16 +00:00
David Rosca
e99f0f953e gallium/auxiliary/vl: Add BT.709 full csc matrix 
Used for converting from full range YUV.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24788>
 2023-08-23 01:01:16 +00:00
Sagar Ghuge
839b03cc06 blorp: Drop unnecessary assertions in blorp_can_hiz_clear_depth 
We already checks for the alignment and the multislice surface, we don't
need to add assertions around those two.

fixes: 37fcbb375c ("blorp: Disable unaligned partial HIZ fast clears for HIZ_CCS too")
closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9684

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24837>
 2023-08-23 00:35:07 +00:00
Rob Clark
39f26642d6 util: Decouple disk cache from EGL_ANDROID_blob_cache 
Just because the user / system-integrater doesn't want shader disk
cache, doesn't mean they don't want EGL_ANDROID_blob_cache to work.
We've kind of already solved this for the android case, so just
generalize that solution.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9520
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24636>
 2023-08-23 00:04:16 +00:00
Emma Anholt
5bd0750921 intel/fs: Simplify compute_start_end(). 
Now that we have moved the screening up, we can simplify the code.  No
change in shader-db steam performance, n=10.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>
 2023-08-22 23:34:30 +00:00
Emma Anholt
2b01246f49 intel/fs: Move the defin[]/defout[] screening up to livein[]/liveout[] setup. 
This keeps us from having to run the loop to propagate up quite so much.

steam shader-db time -1.86356% +/- 0.941498% (n=10).  There's a small
scheduling effect, since previously the scheduler wasn't considering
defin/defout:

cycles helped:   shaders/closed/steam/amnesia-the-dark-descent/high/241.shader_test FS SIMD16: 11428 -> 11422 (-0.05%) (scheduled: scheduled)
cycles helped:   shaders/humus-volumetricfogging2/1.shader_test FS SIMD32: 13832 -> 13800 (-0.23%) (scheduled: scheduled)
cycles helped:   shaders/tesseract/479.shader_test FS SIMD32:      9330 -> 8644 (-7.35%) (scheduled: scheduled)

cycles HURT:   shaders/robclark-shaders/android/angle/aztec_ruins/36.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/57.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/54.shader_test FS SIMD32: 7870 -> 7940 (0.89%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/android/angle/aztec_ruins/30.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/51.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/48.shader_test FS SIMD32: 8726 -> 8808 (0.94%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_4_off/129.shader_test TCS SIMD8: 3911 -> 3979 (1.74%) (scheduled: scheduled)
cycles HURT:   shaders/robclark-shaders/gfxbench5/gl_4_off/109.shader_test TCS SIMD8: 3911 -> 3979 (1.74%) (scheduled: scheduled)

total cycles in shared programs: 313096438 -> 313096306 (<.01%)
cycles in affected programs: 92200 -> 92068 (-0.14%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>
 2023-08-22 23:34:30 +00:00
Emma Anholt
ed4e1becea intel/fs: Move defin/defout setup to the start of the loop. 
Refactor for the next commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24702>
 2023-08-22 23:34:30 +00:00
Daniel Schürmann
7e246f7f2b nir/opt_move: fix handling of if-condition 
By accident, this used the parent of the nir_src which is a nir_if
instead of the parent of the SSA value.

Totals from 10814 (8.10% of 133461) affected shaders: (GFX11)
Instrs: 21759185 -> 21757190 (-0.01%); split: -0.02%, +0.01%
CodeSize: 112320272 -> 112316008 (-0.00%); split: -0.02%, +0.01%
SpillSGPRs: 11220 -> 11212 (-0.07%)
SpillVGPRs: 911 -> 903 (-0.88%); split: -1.54%, +0.66%
Latency: 258334759 -> 258316073 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 31428650 -> 31426394 (-0.01%); split: -0.02%, +0.01%
VClause: 309119 -> 309090 (-0.01%); split: -0.01%, +0.01%
SClause: 657028 -> 657150 (+0.02%); split: -0.03%, +0.04%
Copies: 1434209 -> 1432420 (-0.12%); split: -0.28%, +0.15%
Branches: 481804 -> 481801 (-0.00%)
PreSGPRs: 829995 -> 829966 (-0.00%)
PreVGPRs: 758249 -> 758253 (+0.00%)

Fixes: 8a78706643 ('nir: refactor nir_opt_move')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24695>
 2023-08-22 21:05:18 +00:00
Alyssa Rosenzweig
f9e5534182 nir/lower_gs_intrinsics: Remove end primitive for points 
EndPrimitive() for points is entirely pointless, so just remove it when lowering
EndPrimitive to simplify the IR. This is (maybe) an optimization everywhere, and
will be relied on for correctness on Asahi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24798>
 2023-08-22 20:24:40 +00:00
Alyssa Rosenzweig
8c7629524e nir/print: Print access qualifiers for intrinsics 
Instead of printing an opaque integer that needs to be manually decoded.
Example output:

    32x4   %7 = @image_load (%4 (0x0), %6, %5 (0x0), %4 (0x0)) (image_dim=2D, image_array=false, format=r8g8b8a8_snorm, access=readonly|reorderable, range_base=0, dest_type=float32)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24798>
 2023-08-22 20:24:40 +00:00
Caio Oliveira
48b86a877f compiler/types: Use smaller keys for explicit_matrix_types table 
Instead of using the name as key, use a shorter struct type.
Only build a name string if we are adding a new entry to the table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>
 2023-08-22 18:52:15 +00:00
Caio Oliveira
fd1da0f7f5 compiler/types: Extract get_explicit_matrix_instance() function 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>
 2023-08-22 18:52:15 +00:00
Caio Oliveira
b248740e30 compiler/types: Use smaller keys for array_types table 
Instead of building a string, build a short struct type and use
that as key.  The only caveat here is ensure there either there's
no internal padding or the internal padding is always the same.
Use a static assert to ensure we are in the former case.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>
 2023-08-22 18:52:15 +00:00
Caio Oliveira
d4fcc97a3f compiler/types: Use ralloc for the key in array_types 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23281>
 2023-08-22 18:52:15 +00:00
Eric Engestrom
566c919df8 ci/deqp: backport fix for dEQP-EGL.functional.wide_color.*_888_colorspace_* 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24808>
 2023-08-22 18:12:08 +00:00
norablackcat
f744c114d1 rusticl: add cl_khr_expect_assume 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Andrey Alekseenko <al42and@gmail.com>
Tested-by: Yifeng Li <tomli@tomli.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23115>
 2023-08-22 17:28:05 +00:00
norablackcat
25bc3d2824 spirv/nir_to_spirv: add expect assume op codes 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23115>
 2023-08-22 17:28:05 +00:00
Emma Anholt
37fcbb375c blorp: Disable unaligned partial HIZ fast clears for HIZ_CCS too. 
Fixes MSAA scissored fast clears under zink and ANGLE.

Fixes: e488773b29 ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24225>
 2023-08-22 16:34:52 +00:00
Konstantin Seurer
7aee3ba36d radv: Stop updating the stack_size in insert_rt_case 
There are two paths that call insert_rt_case:
- Traversal shader: The stack size is ignored.
- Monolithic raygen shader: The stack sizes of the inlined shaders are
                            accounted for in compute_rt_stack_size.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
bdec044c88 aco: Do not fixup registers if there are no shader calls 
Frees up some registers when using monolithic compilation.

Quake II RTX and Control (with monolithic compilation):

Totals from 10 (29.41% of 34) affected shaders:
MaxWaves: 77 -> 98 (+27.27%)
Instrs: 49047 -> 48984 (-0.13%); split: -0.16%, +0.03%
CodeSize: 260420 -> 259880 (-0.21%); split: -0.25%, +0.04%
VGPRs: 1328 -> 1104 (-16.87%)
Latency: 477134 -> 479377 (+0.47%); split: -0.05%, +0.52%
InvThroughput: 137763 -> 114108 (-17.17%)
VClause: 1318 -> 1286 (-2.43%); split: -2.66%, +0.23%
SClause: 1295 -> 1293 (-0.15%); split: -0.54%, +0.39%
Copies: 7838 -> 7782 (-0.71%); split: -0.82%, +0.10%
Branches: 2592 -> 2589 (-0.12%)
PreSGPRs: 874 -> 796 (-8.92%)
PreVGPRs: 1283 -> 1013 (-21.04%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
ec708c26ef radv/rt: Split stage initialization and hashing 
The dependency chain is: init stages -> compute pipeline key -> hash
stages.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
f3e2900c59 radv/rt: Insert rt_return_amd before lowering shader calls 
Also skips running nir_lower_shader_calls for the traversal shader. This
will be used to skip the pass and the rt_return_amd insertion for
monolithic raygen shaders.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
774421f11e radv/rt: Add and use radv_build_traversal 
Moves most of the build code to a helper which will be useful for adding
inline traversal.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
2d7965dbff radv/rt: Do not apply stack_ptr for non-recursive stages 
stack_ptr is set to 0.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
Konstantin Seurer
d174a71db8 radv/rt: Remove some dead code 
- call_idx_base was used for resume shaders in the shader call loop
- hit attribs are lowered elsewhere
- stack_size is set in radv_pipeline_rt.c

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24809>
 2023-08-22 15:46:29 +00:00
M Henning
10bbe17253 nv/codegen: Remove Function::buildDefSets 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>
 2023-08-22 10:42:24 -04:00
M Henning
bf48f7ca97 nv/codegen: Delete periodicMask32 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>
 2023-08-22 10:42:24 -04:00
M Henning
eae6800ec3 nv/codegen: Delete unused OP_CONSTRAINT 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>
 2023-08-22 10:42:24 -04:00
M Henning
dcec14c51e nv50_ir_ra: Delete unused functions 
Wrap the file in an anonymous namespace and delete any code that
gcc warns is unused.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24791>
 2023-08-22 10:42:24 -04:00