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Author SHA1 Message Date
Karol Herbst
d5da434851 nir/opt_sink: add load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
535e617ccd nir/lower_alu: support 8 and 16 bit bit_count 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Daniel Schürmann
c4a38c6583 aco/spill: don't remove spilled phis 
They will be removed during register allocation.

Few changes due to different phi order.
Totals from 14 (0.02% of 79395) affected shaders: (GFX11)

Instrs: 315724 -> 315675 (-0.02%); split: -0.02%, +0.01%
CodeSize: 1673608 -> 1673268 (-0.02%); split: -0.03%, +0.00%
Latency: 3194243 -> 3189025 (-0.16%); split: -0.19%, +0.03%
InvThroughput: 638369 -> 637323 (-0.16%); split: -0.19%, +0.03%
VClause: 5716 -> 5714 (-0.03%)
Copies: 37786 -> 37748 (-0.10%); split: -0.13%, +0.03%
Branches: 10469 -> 10454 (-0.14%); split: -0.16%, +0.02%
VALU: 182498 -> 182454 (-0.02%); split: -0.03%, +0.00%
SALU: 36038 -> 36046 (+0.02%); split: -0.01%, +0.04%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
634051f913 aco/live_var_analysis: ignore dead phis 
Since we don't emit code for dead phis, we also don't
have to keep their operands around.

Totals from 44 (0.06% of 79395) affected shaders: (GFX11)

MaxWaves: 648 -> 650 (+0.31%)
Instrs: 449898 -> 449120 (-0.17%); split: -0.18%, +0.00%
CodeSize: 2395000 -> 2389300 (-0.24%); split: -0.24%, +0.00%
VGPRs: 5504 -> 5468 (-0.65%)
Latency: 9005058 -> 9000966 (-0.05%); split: -0.07%, +0.03%
InvThroughput: 2154567 -> 2139095 (-0.72%); split: -0.77%, +0.06%
VClause: 8362 -> 8354 (-0.10%)
SClause: 9135 -> 9134 (-0.01%)
Copies: 60678 -> 60118 (-0.92%); split: -0.93%, +0.01%
Branches: 14379 -> 14385 (+0.04%)
PreSGPRs: 3877 -> 3863 (-0.36%)
PreVGPRs: 6318 -> 6286 (-0.51%)
VALU: 266975 -> 266301 (-0.25%); split: -0.25%, +0.00%
SALU: 52741 -> 52667 (-0.14%); split: -0.15%, +0.01%
VMEM: 16140 -> 16132 (-0.05%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
708e1a73f5 aco/live_var_analysis: slightly refactor handling of additional register demand for Operand copies 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
5cfa5b784b aco: remove get_demand_before() 
The register demand before executing an instruction is now included
in the instruction's register demand and this function is unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
09f1c40f2e aco: track and use the live-in register demand per basic block 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
001c8caae0 aco: calculate register demand per instruction as maximum necessary to execute the instruction 
Previously, the register demand per instruction was calculated as the number of
live variables in the register file after executing an instruction plus additional
temporary registers, necessary during the execution of the instruction.
With this change, now it also includes all variables which are live right before
executing an instruction, i.e. killed Operands.

Care has been taken so that the invariant

register_demand[idx] = register_demand[idx - 1] - get_temp_registers(prev_instr)
                        + get_live_changes(instr) + get_temp_registers(instr)

still holds.

Slight changes in scheduling:

Totals from 316 (0.40% of 79395) affected shaders: (GFX11)

Instrs: 301329 -> 300777 (-0.18%); split: -0.31%, +0.12%
CodeSize: 1577976 -> 1576204 (-0.11%); split: -0.21%, +0.10%
SpillSGPRs: 448 -> 447 (-0.22%)
Latency: 1736349 -> 1726182 (-0.59%); split: -2.01%, +1.42%
InvThroughput: 243894 -> 243883 (-0.00%); split: -0.03%, +0.03%
VClause: 6134 -> 6280 (+2.38%); split: -1.04%, +3.42%
SClause: 6142 -> 6137 (-0.08%); split: -0.13%, +0.05%
Copies: 14037 -> 14032 (-0.04%); split: -0.56%, +0.52%
Branches: 3284 -> 3283 (-0.03%)
VALU: 182750 -> 182718 (-0.02%); split: -0.04%, +0.03%
SALU: 18522 -> 18538 (+0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Daniel Schürmann
4c2f231cc0 aco/spill: Unconditionally add 2 SGPRs to live-in demand 
Due to undefined Operands, it might not be enough to check the
predecessors' register demand.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Daniel Schürmann
26c58ca9de aco/scheduler: fix register_demand validation debug code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Rhys Perry
e3ffc244f5 aco: skip continue_or_break LCSSA phis when not needed 
Fixes:
//exec is empty here
loop {
   %1:s[16-17] = ...
   if () {
      break
   }
   %2:s[16-17] = ...
   continue_or_break
}
%3 = phi %1, undef
//because of the undef, %2 can use s[16-17] and overwrite the address
load(%3:s[16-17])

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: bbe4652430 ("aco: create lcssa phis for continue_or_break loops when necessary")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11333
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29838>
 2024-06-26 09:10:54 +00:00
Julian Orth
77759f7683 egl/wayland: ignore unsupported driver configs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29904>
 2024-06-26 06:56:39 +00:00
Jianxun Zhang
3589035d61 iris: Disable predraw resolve (xe2) 
Fixes piglit test:
arb_texture_barrier-blending-in-shader 32 1 1 64 7 -auto -fbo

src/intel/blorp/blorp_genX_exec.h:910: blorp_emit_ps_config:
Assertion `!"" "Invalid fast clear op"' failed.

Suggested by Kenneth Graunke <kenneth@whitecape.org>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
dc26ad1e86 anv: Update synchronization of fast clear (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
930ea030ed isl: Initialize the last usage in isl_encode_aux_mode[] (xe2) 
The ISL_AUX_USAGE_STC_CCS is the last defined usage. We could
get a random value from isl_encode_aux_mode[] once it is passed
as index if its element is not initialized.

Explicit initialization of ISL_AUX_USAGE_HIZ_CCS_WT is added too.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
9d3ce65628 blorp: Don't convert ccs_e formats for copy (xe2) 
Fix:
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear

blorp_blit.c:2770: get_ccs_compatible_copy_format:
Assertion `!"" "Not a compressible format"' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
255889a795 isl: Remove restriction of CCS_E support on formats (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
31b48fd041 iris: Workaround: Don't allocate compressed bo from cache (xe2) 
There should be some deeper causes to dig out. The bo-caching
system shouldn't affect the compression by design.

Fixes:
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear_mipmap_linear

The two cases can pass if we run them respectively. But once they
are fed to glcts in a test case list file (test.list) to run together,
the second test case hangs for a while and eventually fails, regardless
which of them is the second.

./glcts --deqp-caselist-file=test.list

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
8a815c83c2 iris: Update synchronization of fast clear (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
6073f091bb anv: Disable PAT-based compression on depth images (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
b6f9702cf1 iris: Disable PAT-based compression on depth surfaces (xe2) 
Fix: Piglit
PIGLIT_PLATFORM="gbm" piglit/bin/getteximage-depth -auto -fbo

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
e835b53a03 anv: Don't enable compression on external bos (xe2) 
Fix:

dEQP-VK.synchronization.cross_instance.suballocated.
write_draw_indexed_read_blit_image.image_128x128_r16
_uint_binary_semaphore_fence_fd

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
9cd97b6137 iris: Add more restrictions on compression (Xe2) 
Also move the declaration of a local variable to where
it is going to use.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
0b75f89f57 anv: Don't enable compression with modifiers (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
66fa1c5ddd iris: Limit FCV_CCS_E to platforms that enable it 
We want to keep aux state always in compressed and no clear,
but the write behavior of FCV will change it to compressed and
clear. Reuse old CCS_E on Xe2 to workaround it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8785

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
df006bba02 iris: Update aux state for color fast clears (xe2) 
The texturing and rendering preparation functions restrict
fast clear support in some cases to account for limitations
on prior platforms. Instead of updating those checks to avoid
resolves on Xe2, we can bypass them by representing the aux
state of a fast-cleared surface as compressed-no-clear. This
is valid because there is no longer a bit pattern which
references a clear value stored outside of the aux surface.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
1c92b31888 intel/genxml,blorp,common: Update 3DSTATE_PS command (xe2) 
From Bspec 56423 (r58507), the legacy full resovling and
partial resolving options are gone since Xe2. They also
cause hang on Xe2 if not disabled.

Some suggested code from Nanley Chery <nanley.g.chery@intel.com> is
included.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
4dfc3367fc blorp: Pass down fast clear color value (xe2) 
Also add a quote of Bspec for previous platforms.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
3269d505e7 blorp: Get fast clear rectangle of non-MSAA surfaces (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
3b89bdb96e isl: Don't set clear values or their address (xe2) 
The render surface state doesn't have these features any
more since Xe2.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Qiang Yu
93f790b04a nir: fix clip cull distance lowering metadata preserve 
indirect store lowering will use if/else which changes
the control flow of the shader.

Fixes: 110887de2b ("nir: Add a new pass to lower array dereferences on vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29894>
 2024-06-26 01:22:12 +00:00
Qiang Yu
09b4ba27a3 nir: fix lower array to vec metadata preserve 
indirect store lowering will change control flow,
so we should not preserve control flow metadate
when it's present.

Fixes: 35b8f6f40b ("nir: Add a new pass to lower array dereferences on vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29894>
 2024-06-26 01:22:12 +00:00
Jianxun Zhang
7be1912625 isl: Update render CMF mapping (xe2) 
Update mapping between render target surface formats and
compression formats.

Some preexisting correct mappings are also re-ordered to
the order of types in the spec for an easier verification
(top to bottom and left to right).

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Jordan Justen
a985576755 isl: Implement isl_get_render_compression_format for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Jordan Justen
bb6e8cab79 isl: Move isl_get_render_compression_format in isl_genX_helpers.h 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Ian Romanick
2bbd0fd9da intel/brw/xe2+: Add LNL cooperative matrix configurations 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
6b678d32cb nir: dpas_intel second source can have different number of components 
The number of components for the second source is -1 to avoid validation of
its value. Some supported configurations will have the component count of
that matrix different than the others.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
556e78f737 intel/brw/xe2+: Allow vec16 for cooperative matrix 
Xe2 will allow a B matrix large enough that it will be stored in a
vec16.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
b6236dd8f3 intel/brw/xe2+: Adjust DPAS lowering to DP4A to accommodate larger GRF and SIMD16 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
77ef241577 intel/brw/xe2+: Scale size_written by reg_unit for DPAS 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
e368b8e01b intel/brw/xe2+: Adjust size_read() for DPAS 
v2: Remov "DG2" from a comment because it applies to DG2 and
Xe2. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
b051602754 intel/brw/xe2+: Catch invalid uses of writes_accumulator earlier 
It turns out the problem I was trying to catch in be4fa59a72
("intel/brw: Clear write_accumulator flag when changing the
destination") also came from the DPAS lowering pass itself. Checking for
invalid uses of the feature in fs_validate helped detect the problem.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
7a773ac53e intel/brw: Major rework of lower_cmat_load_store 
The original goal was to get rid of a bunch of the magic constants
sprinkled through the function. Once I did that, I realized that there
was a lot my symmertry between the row-major and column-major paths
possible.

It's +6 lines of code, but about 15 of those lines are comments
explaining things that were not obvious in the original code.

v2: Save duplicated condition in a variable with a meaningful
name. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:16:48 -07:00
Ian Romanick
ea6e10c0b2 intel/brw: Temporarily disable result=float16 matrix configs 
Even though the hardware does not naively support these configurations,
there are many potential benefits to advertising them. These
configurations can theoretically use half the memory bandwidth for loads
and stores. For large matrices, that can be the limiting in performance.

The current implementation, however, has a number of significant
problems.

The conversion from float16 to float32 is performed in the driver during
conversion from NIR. As a result, many common usage patterns end up
doing back-to-back conversions to and from float16 between matrix
multiplications (when the result of one multiplication is used as the
accumulator for the next).

The float16 version of the matrix waste half the possible register
space. Each float16 value sits alone in a dword. This is done so that
the per-invocation slice of an 8x8 float16 result matrix and an 8x8
float32 result matrix will have the same number of elements. This makes
it possible to do straightforward implementations of all the unary_op
type conversions in NIR.

It would be possible to perform N:M element type conversions in the
backend using specialized NIR intrinsics. However, per #10961, this
would be very, very painful. My hope is that, once a suitable resolution
for that issue can be found, support for these configs can be restored.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 13:52:12 -07:00
Juston Li
33dd38f9d5 anv/android: set ANV_BO_ALLOC_EXTERNAL for imported AHW 
This fixes some cacheline flush artifacts

Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29882>
 2024-06-25 20:21:27 +00:00
Daniel Stone
9eeaa4618f egl/gbm: Enable RGBA configs 
Doing this is harmless since we operate on an allowlist of pipe_configs
anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Daniel Stone
94e15d0f64 egl/surfaceless: Enable RGBA configs 
Doing this is harmless since we operate on an allowlist of pipe_configs
anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Daniel Stone
5ca85d75c0 dri: Fix BGR format exclusion 
The check we had for BGR vs. RGB formats was testing completely the
wrong thing. Fix it so we can restore the previous set of configs we
expose to the frontend, which also fixes surfaceless platform on s390x.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: ad0edea53a ("st/dri: Check format properties from format helpers")
Closes: mesa/mesa#11360
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Job Noorman
8f2533c356 ir3: set rounding mode for all floating point conversions 
The rounding mode was only set for a subset of floating point
conversions. This patch sets it for all of them.

Fixes all the dEQP-VK.*.float_controls.* CTS tests.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29843>
 2024-06-25 17:00:59 +00:00
Job Noorman
93db751c63 ir3: print rounding mode for cov 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29843>
 2024-06-25 17:00:59 +00:00