Commit Graph

76955 Commits

Author SHA1 Message Date
Matt Turner
61b10b4eb7 i965: Use foreach_in_list_reverse_safe() macro.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-03-12 19:23:50 -08:00
Jason Ekstrand
98d58e7320 nir/clone: Add support for cloning a single function_impl
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
036b209484 nir/validate: Better function validation
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
f86f3c90aa nir/print: Better function argument printing
Since we aren't going to put the function parameters or the return variable
in the list of locals, it won't get a proper declaration.  This changes
nir_print to print the type along with each parameter or return variable.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
13969565f9 nir/print: Factor variable name lookup into a helper
Otherwise, we have a problem when we go to print functions with arguments
because their names get added to the hash table during declaration which
happens after we print the prototype.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
e4bebe8a02 nir: Create function parameters in function_impl_create
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
066d3c115e nir: Add a helper for creating a "bare" nir_function_impl
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
2ef4754a20 nir: Add a new "param" variable mode for parameters and return variables
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Jason Ekstrand
41ae553fda nir/glsl: Remove dead function parameter handling code
NIR has never been used on IR where we haven't already done function
inlining so this code has been dead from the beginning.  Let's just get rid
of it for now.  We can always put it back in if we decide to use NIR for
function inlining at some point in the future.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-12 15:48:36 -08:00
Boyuan Zhang
6cf120ec77 st/va: add HEVC main 10 profile
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-11 22:33:56 -05:00
Boyuan Zhang
06c862d67d radeon/video: enable HEVC main 10 decode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-11 22:33:56 -05:00
Boyuan Zhang
8be9efcce7 radeon/uvd: handle HEVC main 10 decode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-11 22:33:56 -05:00
Ben Widawsky
d1ab544bb8 i965/chv: Display proper branding
"Braswell" is a Cherryview based *thing*. It unfortunately requires extra
information to determine its marketing name. Unlike all previous products, and
hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to
brand string.

I put up a fight about adding any complexity to our GL renderer string code for
a very long time. However, a wise man made a comment to me that I couldn't argue
with: if a user installs Windows on their hardware, the brand string should be
the same as what we display in Linux. The Windows driver apparently does this
check, so we should too.

Note that I did manage to find a good use for this info anyway in the compute
shader thread counts.

v2: memcpy instead of strncpy, and some minor changes (Matt)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
2016-03-11 11:17:28 -08:00
Ben Widawsky
5e6a43a001 i965/chv: Update lower min for CS threads
We have better information now, and 28 was not a valid thing to support. 6 EUs
per sublice with 7 threads per EU is the minimum supported config.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
2016-03-11 11:17:28 -08:00
Ben Widawsky
3dc3dbc8d8 i965/chv: Check that compute threads are above threshold
The way we are organizing this code, the statically configured max_cs_threads
should always be the minimum value we actually support (ie. are aware of). As a
result, we can fall back to that if we get invalid numbers from the kernel (ie.
when the query succeeds, but the result is lower than expected).

I was originally planning to use an assert, but there is no reason to be so
mean.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
2016-03-11 11:17:28 -08:00
Ben Widawsky
9dd20b715a i965/chv: Use kernel provided info for max_cs_threads
With the previous patches, the code can find out the actual number of available
compute threads. It is enabled only for Cherryview since that is the only
platform I know for a fact has shipped devices which can benefit from this.  It
seems like other platforms /might/ benefit from this because of fused
configurations which /might/ have shipped. Fallback code is still there.

v2: Some minor adjustments from Matt

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com
2016-03-11 11:17:28 -08:00
Ben Widawsky
38eb606884 i965: Query and store GPU properties from kernel
Certain products are not uniquely identifiable based on device id alone. The
kernel exports an interface to help deal with this. This patch merely introduces
the consumer of the interface and makes sure nothing breaks.

It is also possible to use these values for programming GPGPU mode, and I plan
to do that as well.

The interface was introduced in libdrm 2.4.60, which is already required, so it
should all be fine.

v2: Some minor changes recommended by Matt

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-11 11:17:28 -08:00
Nicolai Hähnle
9908b13af6 st/mesa: check that the image unit is valid in st_bind_images
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-11 11:53:40 -05:00
Bas Nieuwenhuizen
417b6721a0 radeonsi: Lazily re-set sampler views after disabling DCC
Clear DCC flags if necessary when binding a new sampler view.

v2: Do not reset DCC flags of bound sampler views.
v3: Check that we have a real texture (Nicolai)

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-11 11:51:15 -05:00
Marek Olšák
af3454cad5 st/mesa: remove ST_NEW_MESA flag (v2)
Only used indirectly when checking dirty.st != 0

v2: also update st_cb_compute.c

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-11 16:07:18 +01:00
Nicolai Hähnle
e502801d98 r600g: clear compressed_depthtex/colortex_mask when binding buffer texture
Found by inspection of the source based on a bisected bug report.

This bug has been in the code for a long time, but the more recent PBO upload
feature exposed it because it leads to more uses of buffer textures.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94388
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-11 08:00:15 -05:00
Ilia Mirkin
f8ea98e4ec st/mesa: add GL_ARB_shader_atomic_counter_ops support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-10 22:36:17 -05:00
Ilia Mirkin
075a5742bf mesa: add GL_ARB_shader_atomic_counter_ops support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-10 22:34:46 -05:00
Ilia Mirkin
a8819fb1ff nvc0: add support for TGSI FMA ops
This will allow the nouveau backend to not try and split up ops that are
fused in GLSL.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-03-10 22:34:28 -05:00
Nicolai Hähnle
59c5508b9a radeonsi: update compressed_colortex_masks when a cmask is created or disabled
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-10 18:22:52 -05:00
Nicolai Hähnle
da68a9b215 radeonsi: move si_decompress_textures to si_blit.c
Since it is all about calling into blitter functions, it makes more
sense here. This change also reduces the size of the interfaces between
.c files.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-10 18:22:49 -05:00
Nicolai Hähnle
f03c9e5692 r600g: update compressed_colortex_masks when a cmask is created or disabled
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-10 18:22:46 -05:00
Nicolai Hähnle
784269aa40 gallium/radeon: notify all contexts when cmasks are enabled/disabled
There is an annoying corner case that I stumbled across while looking into
piglit's arb_shader_image_load_store/execution/load-from-cleared-image.shader_test
(which can be easily adapted to demonstrate the bug without the
ARB_shader_image_load_store extension)

When we bind a texture and then clear it using glClear (by attaching it
to the current framebuffer) for the first time, we allocate a separate
cmask for the texture to do fast clear, but the corresponding bit in
compressed_colortex_mask is not set. Subsequent rendering will use
incorrect data.

Conversely, when a currently bound texture with an existing cmask is
exported leading to that cmask being disabled, the compressed_colortex_mask
bit will remain set, leading to an assertion later on in debug builds.

Since iterating through all contexts and/or remembering where every
texture is bound would be costly, and cmask enable/disable should be
rare, we will maintain a global counter to signal contexts that they
must update their compressed_colortex_masks.

This patch introduces the global counter, and subsequent patches will
do the mask update.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-10 18:22:00 -05:00
Kenneth Graunke
9ea00c6f6b i965: Set a proper _BaseFormat for window system renderbuffers in ES.
intel_alloc_private_renderbuffer_storage did:

   rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);

Unfortunately, internalFormat was usually an unsized format (such as
GL_DEPTH_COMPONENT).  In OpenGL ES, _mesa_base_fbo_format() refuses to
accept unsized formats, and returns 0 rather than a real base format.

This meant that we ended up with a completely bogus rb->_BaseFormat for
window system buffers on OpenGL ES.  All other renderbuffer allocation
functions in intel_fbo.c instead use the mesa_format, and do:

   rb->_BaseFormat = _mesa_get_format_base_format(...);

We can do likewise, using rb->Format.  This appears to work just fine.

dEQP-GLES3.functional.state_query.fbo.framebuffer_attachment_x_size_initial
failed, as it tried to perform a GL_FRAMEBUFFER_ATTACHMENT_DEPTH_SIZE query
on the window system depth buffer.  That query relies on a proper
rb->_BaseFormat being set, so it broke because rb->_BaseFormat was 0 due
to the above bug.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94458
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-03-10 11:23:52 -08:00
Kenneth Graunke
e032e4ad5a glcpp: Fix locations when encounting "#<NEWLINE>".
We were failing to reset our location tracking when encountering a
NEWLINE in the <HASH> state.  Rip the code from the <*>{NEWLINE} rule,
which handles this properly.

Also, update 146-version-first-hash.c to have proper expectations.
When I introduced the test, I didn't verify that the line/column
numbers were correct, and it turns out they varied based on the type
of newline ending.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94447
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-03-10 11:23:26 -08:00
Tim Rowley
84f857bef7 gallium/swr: remove use of BYTE from swr driver
Remove use of a win32-style type leaked from the swr rasterizer.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-03-10 11:20:58 -06:00
Samuel Pitoiset
dad3e5f4ef nvc0: expose SM35 perf counters to AMD_performance_monitor
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:40 +01:00
Samuel Pitoiset
0e511400de nvc0: add driver metrics for SM35 (GK110)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:38 +01:00
Samuel Pitoiset
bf840aa523 nvc0: add MP performance counters for SM35 (GK110)
Because compute support is not enabled by default for these chipsets,
NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable
performance counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:35 +01:00
Samuel Pitoiset
f289e99dee nvc0: explode config of Kepler hardware SM events
This is really verbose but most of the configuration will be reused
for SM35 (GK110).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:32 +01:00
Samuel Pitoiset
a0ce8536b3 nvc0: rework the driver metrics infrastructure
This follows the same design as MP perf counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:29 +01:00
Samuel Pitoiset
41fb87249a nvc0: rework the MP counters infrastructure
This mainly improves how we define the different list of queries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-10 18:20:26 +01:00
Marek Olšák
7b29188a3f egl: clean up typedef madness in the backend API
let's use the dd.h format

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-03-10 18:03:14 +01:00
Iago Toral Quiroga
3e3de9ec0a glsl: report correct number of allowed vertex inputs and fragment outputs
Before we would always report 16 for both and we would only fail if either
one exceeded 16. Now we fail if the maximum for each is exceeded, even if
it is smaller than 16 and we report the correct maximum.

Also, expand the size of to_assign[] to 32. There is code at the top
of the function handling max_index up to 32, so this just makes the
code more consistent.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-03-10 08:48:53 +01:00
Vinson Lee
d46feee697 nouveau: Fix clang reserved-user-defined-literal error.
CXX      codegen/nv50_ir.lo
In file included from codegen/nv50_ir.cpp:28:
./nouveau_debug.h:19:30: error: invalid suffix on literal; C++11 requires a space between literal and identifier
      [-Wreserved-user-defined-literal]
   fprintf(stderr, "%s:%d - "fmt, __FUNCTION__, __LINE__, ##args)
                             ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-03-09 23:00:45 -08:00
Kenneth Graunke
3823b53ff8 mesa: Make glGetInteger64v convert float/doubles to 32-bit integers.
According to the GL 4.4 core specification, section 2.2.2 ("Data
Conversions For State Query Commands"):

"If a command returning integer data is called, such as GetIntegerv or
 GetInteger64v, a boolean value of TRUE or FALSE is interpreted as one
 or zero, respectively. A floating-point value is rounded to the nearest
 integer, unless the value is an RGBA color component, a DepthRange
 value, or a depth buffer clear value. In these cases, the query command
 converts the floating-point value to an integer according to the INT
 entry of table 18.2; a value not in [−1, 1] converts to an undefined
 value."

The INT entry of table 18.2 shows that b = 32, meaning the expectation
is to convert it to a 32-bit integer value.

Fixes:
dEQP-GLES3.functional.state_query.floats.blend_color_getinteger64
dEQP-GLES3.functional.state_query.floats.color_clear_value_getinteger64
dEQP-GLES3.functional.state_query.floats.depth_clear_value_getinteger64

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94456
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-03-09 19:44:18 -08:00
Emil Velikov
3dc2630e45 gallium/radeon: use explicit drm_major, drm_minor check
Just like everywhere else in the radeon codebase.

v2: Don't forget about drm_major == 3 (Alex)

Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-09 17:25:22 +00:00
Emil Velikov
b9c5c4af6d egl/x11: check the return value of xcb_dri2_get_buffers_reply()
... before using it. The function can return NULL, which we should check
prior to refererencing it in the next function(s).

Cc: Fabian Vogt <fvogt@suse.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93667
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2016-03-09 17:25:22 +00:00
Emil Velikov
373f118c6c gallium: do not wrap header inclusion in
Add one missing extern C guard within include/pipe/p_video_enums.h, and
remove the wrapping throughout gallium.

On Haiku one could even use the gallium debug_printf() although
that's another topic.

v2: Leave dbghelp.h as is (Jose)

Cc: Jose Fonseca <jfonseca@vmware.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-09 17:21:39 +00:00
Dieter Nützel
69d389c52f opencl: fix .gitignore for .install-gallium-links
Fixes: 0b6157e971 "install-gallium-links: port changes from install-lib-links"

v2: move this to the top level .gitignore and added Fixes:
    like Emil Velikov <emil.l.velikov@gmail.com> suggested

Signed-off-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-03-09 17:16:52 +00:00
Emil Velikov
f3e23ead53 egl: remove remnants of MESA_drm_display
Last set in st/egl, unused in mesa-demos and superseded by
EGL_KHR_platform_gbm.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-03-09 17:16:51 +00:00
Emil Velikov
2295a4b1e1 egl: remove final pieces of KHR_vg_parent_image
Similar to previous commit - unused/unset for a long time.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-03-09 17:16:51 +00:00
Emil Velikov
c85544a10c glapi: remove the final function offset tags
A commit earlier this year reworked out python scripts to use a separate
file for these. Followed by removing support from the parser, and
removing all of the offset tags.

Seems like we either missed a few, or people added them by mistake.
Either way let's nuke the ones that are still around.

Cc: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-03-09 17:16:51 +00:00
Emil Velikov
3ffab9a89c winsys/amdgpu/addrlib: do not wrap header inclusion in extern "C"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-09 17:16:51 +00:00
Emil Velikov
a07192bd63 mesa/main: do not wrap header inclusion in extern "C"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-03-09 17:16:51 +00:00