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Author SHA1 Message Date
Christopher Michael
fa939898bb broadcom: fix issue of ‘addr’ is used uninitialized 
This small patch fixes an issue where 'addr' is used uninitialized if
the assert gets removed due to compiling release code and thus
returning uninitialized 'addr'

v2: Modified based on initial review:
    a) No need to initialize the 'addr' and 'ret' variables
    b) Fix 'ret' variable to be proper type based on hw->get_mem return value

v3: Modified based on additional review:
    a) Since both the simulator and mesa have their own version of
'unreachable()' and we cannot use ASSERT for the 'ret' value here,
just use a (void) ret after the assert

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29434>
 2024-05-30 20:40:26 +00:00
Ruijing Dong
c1e52baf30 radeonsi/vcn: enable roi feature for vcn5 
Compared to vcn4, qp map unit is a 32bit number,
vcn5 uses 16bit integer number, in addition to
that it has 2 unit alignment requirement(32 bit
alignment) and each qp value needs left shift 7 bits.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
83d0189288 radeonsi/vcn: enable av1 encoding in vcn5 
Have logic to handle tile allocation
according to vcn5's capability, if the
tile allocation is out of the limit, will
re-adjust the tile parameters.

re-construct frame header and obu instruction
logic. And add av1 encode params requried
for vcn5.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
6d90a1baa5 radeonsi/vcn: add header files for vcn5 av1 tile 
Update header files for av1 tile and delta qp.
vcn5 needs driver and applcation to manage that
while in vcn4 they are managed in FW.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
5860d4348a frontends/va: parsing uniform_tile_spacing flag 
in order to keep uniform_tile_spacing flag, parsing
it in frontends/va.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
250c89dd6d radeonsi/vcn: share functions between vcn4/vcn5 
change some local functions to be shared.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
0712a5ef96 radeonsi/vcn: apply cdef mode to vcn5 
When cdef_bits exist from external, use explicit mode,
otherwise, use default cdef mode.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
80d3e84b81 radeonsi/vcn: add cdef modes for vcn5 encoding 
default mode is the cdef id is managed by FW.
explicit mode is using external cdef id.

Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Ruijing Dong
e20acd605e radeonsi/vcn: correct tile_size_bytes_minus1 
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>
 2024-05-30 20:12:37 +00:00
Sagar Ghuge
57307df766 iris: Load 32-bit MMIO PREDICATE register from buffer 
We are writing 32-bit register value to buffer and were reading back
64-bit value back into two register. We don't need to read the second
register in this case.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29389>
 2024-05-30 19:46:42 +00:00
Mike Blumenkrantz
2aaa6ebba1 build/amd: add amd-use-llvm build option 
this allows amd drivers to disable llvm support while still allowing
llvmpipe/lavapipe to be built

by disabling llvm support in amd drivers, the load times for these drivers
decreases by 5-10ms

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28969>
 2024-05-30 19:05:00 +00:00
Amit Pundir
38dfbae116 android: Fix zink build failure 
Otherwise we run into following build error on Android:

    ld.lld: error: undefined symbol: galliumvk_driver_extensions

Fixes: cfa955ed78 ("glx/egl: fix LIBGL_KOPPER_DISABLE")
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29475>
 2024-05-30 18:16:59 +00:00
Eric Engestrom
21138f418c etnaviv/ci: skip VK piglit tests 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29488>
 2024-05-30 18:08:45 +00:00
Eric Engestrom
3ec480825e panfrost: mark tests as fixed 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29487>
 2024-05-30 17:47:32 +00:00
Eric Engestrom
fbb306df15 panfrost/ci: add missing genxml trigger path 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29487>
 2024-05-30 17:47:32 +00:00
Samuel Pitoiset
72b1fa2ba3 radv: fix configuring the number of patch control points on GFX6 
Fixes: bf936d0291 ("radv: update configuring the number of patch control points on GFX12")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29485>
 2024-05-30 17:18:54 +00:00
José Roberto de Souza
07855b0431 intel: Compute the optimal preferred SLM size per subslice 
Up to now preferred SLM size was being set to maximum preferred SLM
size for GFX 12.5 platforms and to workgroup SLM size for Xe2 but
neither of those values are the optimal.
The optimal value is:
<number of workgroups that can run per subslice> * <workgroup SLM size>

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
fd368f5521 anv: Set maxComputeSharedMemorySize value for Xe2 platforms 
Xe2 platforms allows for a larger compute shared memory(SLM).
For LNL this limit is 160KB but due to a workaround the limit is 128K.

BSpec: 71053
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
ddda68bbf5 intel: Set preferred SLM allocation size >= than SLM size for Xe2 
Xe2 has 2 requirements for preferred SLM size:
- this value needs to be >= then SLM size
- this value must be less than shared SLM/L1$ RAM in the sub-slice of platform

Also Xe2 don't have the special '0' encode that sets preferred SLM
allocation size to the maximum supported.
So here setting a value that is equal or larger than SLM size.

It was always setting SLM_ENCODES_128K for LNL A0 stepping probably
because of Wa_16018610683 but this restriction applies to all Xe2
platforms, also because of the first restriction mentioned here
this workaround is not being properly implemented, will fix that
in the next patch.

We should have a formula to calculate a preferred SLM allocation size
for gfx125 and Xe2 platfoms but until that this is enough to fix at
least the applications and tests below on LNL:
- GFXBench Aztec Ruins VK
- GravityMark VK
- Wildlife Extreme VK
- 5 crucible tests

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
c4478ab4e3 intel/dev: Add function to get the number of EUs per subslice 
This value will be needed to compute preferred SLM size.
User will be added in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
df3ce7add2 intel/dev: Use topology variables to calculate strides in Xe KMD 
Lets avoid hard-coded values as much as possible.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
e0af347791 intel/common: Implement preferred SLM encode 
Preferred SLM has a different encode than SLM allocation size so
adding a function just to encode it, functions call to this new
function will be added in the next patches.

BSpec: 64042
BSpec: 68700
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
f1ffbd4f51 intel/common: Implement Xe2 SLM encode 
Xe2 SLM encode don't follow power of two so it needs a table doing
the kb size to value encode.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
José Roberto de Souza
f5f71bae02 intel: Move slm functions from brw_compiler.h to intel_compute_slm.c/h 
This functions were inlined in a header and duplicated between brw and
elk.
That would be enough reasons to move to a C file but next patches
will add more code to support Xe2 platforms, what would cause more
code to be inlined, duplicating even more code and increasing lib
size.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28910>
 2024-05-30 16:46:16 +00:00
Eric Engestrom
357dde47a5 docs/calendar: add 24.2 branchpoint and release candidates schedule 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29484>
 2024-05-30 16:30:34 +00:00
Eric R. Smith
d91d2c275e panfrost: change default rounding mode for samplers 
The SamplerDescriptor structure has a field which describes how
floating point coordinates should be converted to fixed point.
Setting this to "true" (which causes round to nearest even) fixes
a failing CTS test.

The CTS test in question is:
dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_float_color

The OpenGL spec is somewhat vague about how rounding is to be
performed, so it appears both settings should be legal; this may
indicate a problem with the CTS. Nevertheless "round to nearest even"
is probably a better default and since it fixes the failing test we
may as well use it.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29464>
 2024-05-30 13:35:26 +00:00
Timur Kristóf
ad033506aa radv: Ignore mediump IO flag. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29435>
 2024-05-30 12:57:20 +00:00
Timur Kristóf
0ea2bad74d nir/lower_io: Add option to implement mediump as 32-bit. 
For drivers that don't lower mediump shader inputs / outputs
to 16-bit, it's better to ignore the mediump flag completely,
letting mediump inputs / outputs work like normal 32-bit IO.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29435>
 2024-05-30 12:57:20 +00:00
Timur Kristóf
be49b02f05 radv: Properly link TCS->TES IO again. 
This commit makes RADV TCS->TES IO great again.

Fossil DB stats on Navi 21:

Totals from 2634 (3.32% of 79395) affected shaders:
MaxWaves: 56336 -> 56450 (+0.20%)
Instrs: 1670370 -> 1667819 (-0.15%); split: -0.22%, +0.06%
CodeSize: 8675476 -> 8643176 (-0.37%); split: -0.39%, +0.01%
VGPRs: 126776 -> 126608 (-0.13%)
LDS: 10444288 -> 10617856 (+1.66%)
Inputs: 30910 -> 25426 (-17.74%)
Outputs: 27000 -> 21516 (-20.31%)
Latency: 9403584 -> 9391648 (-0.13%); split: -0.25%, +0.12%
InvThroughput: 2127488 -> 2127180 (-0.01%); split: -0.13%, +0.12%
VClause: 33495 -> 34413 (+2.74%); split: -0.32%, +3.06%
SClause: 27905 -> 27879 (-0.09%); split: -0.30%, +0.20%
Copies: 82562 -> 83007 (+0.54%); split: -0.32%, +0.86%
PreSGPRs: 91029 -> 91014 (-0.02%)
PreVGPRs: 108505 -> 108473 (-0.03%); split: -0.06%, +0.03%
VALU: 1088113 -> 1087730 (-0.04%); split: -0.18%, +0.14%
SALU: 182853 -> 179541 (-1.81%); split: -1.82%, +0.01%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29436>
 2024-05-30 12:28:51 +00:00
Timur Kristóf
2cf7f282df ac/nir/tess: Adjust TCS->TES output mapping for linked shaders. 
Instead of relying on driver locations, let's use a prefix sum
of the inputs that the TES reads.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29436>
 2024-05-30 12:28:51 +00:00
Roman Stratiienko
902b142637 turnip/android: Use DETECT_OS_ANDROID in freedreno_rd_output 
ANDROID definition is not available in some cases.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29478>
 2024-05-30 11:58:46 +00:00
Roman Stratiienko
6fee2715ce turnip/android: Use DETECT_OS_ANDROID in tu_device 
ANDROID definition is not available in some cases.

Fixes: 99753001f3 ("turnip: Support AHardwareBuffer")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11242
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29478>
 2024-05-30 11:58:46 +00:00
Samuel Pitoiset
c1373239f2 radv: allow STORAGE for depth formats 
Pass all new VKCTS test coverage for D16/D32.
Tested on PITCAIRN, POLARIS10, VEGA10 and NAVI21.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29239>
 2024-05-30 11:30:23 +00:00
Samuel Pitoiset
f9af8e7a2b radv: do not enable HTILE for depth/stencil storage images 
STORAGE will be allowed for depth-only formats, but HTILE is unlikely
to be supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29239>
 2024-05-30 11:30:22 +00:00
Samuel Pitoiset
b2fd49201e radv: update VS input VGPRs on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
5636af1702 radv: update SDMA resource type on GFX12 
It should be 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
d4d2578e91 radv: update global graphics shader pointers on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
aa0f9e356f radv: update NUM_THREAD_FULL bitfields on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
45b6b0cafb radv: enable GE_CNTL.DIS_PG_SIZE_ADJUST_FOR_STRIP on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
2ac7154189 radv: update configuring VGT_SHADER_STAGES_EN on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
bf936d0291 radv: update configuring the number of patch control points on GFX12 
GFX12 uses VGT_PRIMITIVE_TYPE instead of LS_HS_CONFIG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
d6ae8c689e radv: emit SQ_NON_EVENT packets after drawing with streamout on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
9d50725ffe radv: disallow merging multiple draws into one wave on GFX12 
It's not supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
f25b2d179e radv: update emitting stipple line on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
137b49ecd7 radv: update cache flush emission on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
bd95512e0a radv: do not emulate clear state for shadowed regs on GFX12 
There is no CLEAR_STATE on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
ce6557cc04 aco: adjust loading local invocation ID for GS on GFX12 
It uses gs_vtx_offset[0] instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
06598bc707 radv: update shader input arguments for GS stage on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
10b97836b9 radv: update emitting discard rectangles on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00
Samuel Pitoiset
f518bf1cb0 radv: update binning settings on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
 2024-05-30 11:05:04 +00:00