Commit Graph

63620 Commits

Author SHA1 Message Date
Eric Anholt
66f5c8df06 i965: Generalize the pixel_x/y workaround for all UW types.
This is the only case where a fs_reg in brw_fs_visitor is used during
optimization/code generation, and it meant that optimizations had to be
careful to not move pixel_x/y's register number without updating it.

Additionally, it turns out we had a couple of other UW values that weren't
getting this treatment (like gl_SampleID), so this more general fix is
probably a good idea (though I wasn't able to replicate problems with
either pixel_[xy]'s values or gl_SampleID, even when telling the register
allocator to reuse registers immediately)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 09:49:27 -07:00
Eric Anholt
11bef60d09 i965: Move has_hiz from the slice to the level.
The value depends only on the level, so no need to store the bool per slice.
Shrinks intel_mipmap_slice from 24 bytes to 16, while slotting into an
existing hole in intel_mipmap_level.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2014-05-12 09:49:18 -07:00
Topi Pohjolainen
4dc9c314c8 meta: Refactor configuration of renderbuffer sampling
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
a2952315ac meta: Refactor binding of renderbuffer as texture image
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
ac4db0aa55 meta: Merge compiling and linking of blit program
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
3a43cd0c3e i965/blorp: Expose coordinate scissoring and mirroring
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
4a92ad5531 i965/gen8: Use helper variables for surface parameters
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Ilia Mirkin
8baed87212 nv50,nvc0: fix blit 3d path for 1d array textures
Need to adjust coordinates since the shader receives the array index as
depth in z, but the TEX instruction expects it to be the second
coordinate for a 1D array texture. This fixes fbo-generatemipmap-array.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
4467c0c9fb nv50,nvc0: leave queries on during blit, turn them on for 2d engine
Fixes the new logic of the conditional rendering piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
64a7ddf40d mesa/st: leave current query enabled during glBlitFramebuffer
Also make sure that pipe_blit_info gets zero'd out so that query isn't
accidentally left enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
752ce0affb gallium: add bit to pipe_blit_info to leave current query enabled
Previously the implication was that queries should be disabled during
blits. However glBlitFramebuffer() is supposed to obey the current
query, and this new bit will indicate that to the driver.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
863573b9cb nv50: fix setting of texture ms info to be per-stage
Different textures may be bound to each slot for each stage. So we need
to be able to upload ms parameters for each one without stages
overwriting each other.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
68f47cad0d nv50/ir: make sure to reverse cond codes on all the OP_SET variants
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2 10.1" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Rob Clark
83b4ec03e7 freedreno/a2xx: fix compiler warning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-11 08:58:20 -04:00
Marek Olšák
d9e102b220 radeonsi: prepare depth export registers at compile time
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
9baaa5dd4f radeonsi: simplify depth/stencil export code
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
bd2df40a84 radeon/llvm: add support for non-scalar system values
The sample position is one of them.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
250aa93e23 radeonsi: add and use a helper function for loading constants
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
86035cd88d radeonsi: only count CS space for state atoms if we're going to draw
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
023d367ae6 radeonsi: remove unused variable exports_ps in si_pipe_shader_ps
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
315f3c171d radeonsi: use DRAW_PREAMBLE on CIK
It's the same as setting the 3 regs separately, but shorter, and it also
seems to be required on GFX7.2 and later. This doesn't fix Hawaii.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
58c659703b r600g: simplify framebuffer state size computation
Take the upper bound. The number doesn't have to absolutely correct, only safe.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Kenneth Graunke
155f98d49f Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."
This reverts commit e6967270c7.

Chris Forbes pointed out that this is broken for texture views which
restrict the number of slices.  He committed a better fix which makes
this unnecessary.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-09 20:08:38 -07:00
Emil Velikov
a3e78bab7f egl_dri2: cleanup memory leak in dri2_create_context()
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2014-05-10 02:09:02 +01:00
Emil Velikov
42770ff94e ilo: destroy the mutex, if winsys creation fails
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2014-05-10 02:09:02 +01:00
Emil Velikov
326b8e253e glx/tests: Partially revert commit 51e3569573
C++ does not support designated initializers, thus compilation
is not guaranteed to succeed. Surprisingly gcc 4.6.3 fails to
build the code, while version 4.9.0 compiles it without a hitch.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78403
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
2014-05-10 02:08:36 +01:00
Emil Velikov
e477d12c33 configure: error out if building GBM without dri
Both backends require --enable-dri, and building an empty libgbm
makes little to no sense. Error out at configure to prevent the
user from shooting themselves in the foot.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78225
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-10 02:08:36 +01:00
Chia-I Wu
510465016b mesa: propagate FragDepthLayout to gl_program
The information was lost during linking, causing the layout to be treated as
FRAG_DEPTH_LAYOUT_NONE.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 17:21:53 -07:00
Chris Forbes
417f5ea00d glsl: Rename linker's is_varying_var
Both the ast->IR and linker have functions with this name, but different
behavior.

Rename the linker's version to var_counts_against_varying_limit to be
closer to what it is actually used for.

Suggested by Ian a while back.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-05-10 09:29:13 +12:00
Kenneth Graunke
9584959123 i965: Fix GPU hangs on Broadwell in shaders with some control flow.
According to the documentation, we need to set the source 0 register
type to IMM for flow control instructions that have both JIP and UIP.

Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Tested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-09 14:18:13 -07:00
Tom Stellard
93c2ebbd83 radeonsi: Enable geometry shaders with LLVM 3.4.1
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-05-09 12:16:05 -04:00
Tom Stellard
c5d0008325 configure.ac: Add LLVM_VERSION_PATCH to DEFINES
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-05-09 12:16:05 -04:00
Carl Worth
a96c3bccf6 docs: Import 10.1.3 release notes, andd news item. 2014-05-09 07:52:26 -07:00
Thomas Hellstrom
9306b7c171 st/xa: Fix performance regression introduced by commit "Cache render target surface"
The mentioned commit has the nasty side-effect of turning off accelerated
copies.

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-05-09 08:40:12 +02:00
Tom Stellard
c5f0c98c49 clover: Destory pipe_screen when device does not support compute v2
v2:
  - Make sure screen was successfully created before destroying it.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-05-09 04:33:03 -04:00
Tom Stellard
c650033b86 pipe-loader: Don't destroy the winsys in the sw loader
The screen takes ownership of the winsys, and is responsible for
destroying it.  Users of pipe-loader should make sure they destory
and  screens they've created to avoid memory leaks.

This fixes a crash in clover introduced by
ce6c17c083 where the pipe-loader was
destroying the winsys while a screen was still using it.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-05-09 04:32:54 -04:00
Chris Forbes
23e9f06569 i965/Gen8: Set up layer constraints properly for depth buffers
Same issues as the previous commit fixed for Gen7:
- Bogus physical->logical layer conversion; depth/stencil surfaces
  are still IMS layout on Gen8.
- mt_layer ignored in layered rendering case, which breaks handling
  of views with MinLayer.
- Render target array extent not set correctly for arrays.

I'm not able to test this one since I can't get a Broadwell yet, but
it's the same set of fixes as for Gen7.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 09:46:20 +12:00
Chris Forbes
77d55ef481 i965/Gen7: Set up layer constraints properly for depth buffers
Again, a few problems:
- Layered attachments did not honor MinLayer.
- Non-layered MSAA attachments rendered to the wrong layer due to
  dividing by the layer count. All depth buffers use the IMS layout, so
  the physical layer count == logical layer count.
- Layered attachments were not limited to irb->layer_count, so we could
  render off the end of the texture.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 09:46:19 +12:00
Chris Forbes
9269ea599c i965/Gen8: Set up layer constraints properly for renderbuffers
Fixing the same issues the previous commit does for Gen7.

Note that I can't test this one, since I don't have a Broadwell.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 09:46:19 +12:00
Chris Forbes
dd43900b7b i965/Gen7: Set up layer constraints properly for renderbuffers
There were a few problems here, which mostly just broke layered
rendering into a view:

- Render target view extent was always set to be == depth. This is
  benign for non-layered-rendering, but allows writes off the end of the
  render target for layered rendering, which ends badly.
- Layered rendering did not honor the mt_layer setting, so would not
  properly handle MinLayer being set on a view.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 09:46:19 +12:00
Chris Forbes
cc8c00da88 i965: Fix typo in assert message
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-09 09:46:19 +12:00
Adam Jackson
74388dd24b radeonsi: Don't use anonymous struct trick in atom tracking
I'm somewhat impressed that current gccs will let you do this, but
sufficiently old ones (including 4.4.7 in RHEL6) won't.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2014-05-08 12:05:58 -04:00
Roland Scheidegger
cf93f86957 llvmpipe: change LP_MAX_SHADER_INSTRUCTIONS limit definition.
When the limit was changed to be defined in terms of LP_MAX_SHADER_VARIANTS
(75f1fea14f) when it was increased, this
inadvertently lowered the limit in some branches (that have a lower
LP_MAX_SHADER_VARIANTS number) when merged. So, make sure the limit is always
at least the number it once was.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-08 16:26:49 +02:00
Roland Scheidegger
9af68e9b1d draw: do not use draw_get_option_use_llvm() inside draw execution paths
1c73e919a4 made it possible to not allocate
the tgsi machine if llvm was used. However, draw_get_option_use_llvm() is
not reliable after draw context creation, since drivers can explicitly
request a non-llvm draw context even if draw_get_option_use_llvm() would
return true (and softpipe does just that) which leads to crashes.
Thus use draw->llvm to determine if we're using llvm or not instead (and
make draw->llvm available even if HAVE_LLVM is false so we don't have to put
even more ifdefs).

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-05-08 16:26:49 +02:00
Kenneth Graunke
e6967270c7 i965: Fix depth (array slices) computation for 1D_ARRAY render targets.
1D array targets store the number of slices in the Height field.

Fixes Piglit's spec/!OpenGL 3.2/layered-rendering/clear-color-all-types
1d_array single_level, at least when used with Meta clears.

Cc: "10.2 10.1 10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-05-07 23:42:11 -07:00
Kenneth Graunke
5c399ca8e4 mesa: Fix MaxNumLayers for 1D array textures.
1D array targets store the number of slices in the Height field.

Cc: "10.2 10.1 10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-05-07 23:42:11 -07:00
Kenneth Graunke
ecfc418b68 i965: Enable GL_ARB_texture_view on Broadwell.
This is a port of commit c9c08867ed.
A tiny bit of extra work was necessary to not break stencil texturing.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-07 23:42:11 -07:00
Ilia Mirkin
9d95d64be0 mesa: pass target through to driver when choosing texture format
This only matters for TextureView where the texObj's target has not been
set yet, in all other instances, texObj->target should be the same as
the passed-in target parameter.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-05-07 20:40:46 -04:00
Ilia Mirkin
e7047f2917 nv50/ir/gk110: fix set with f32 dest
Should fix comparison opcodes like SGE/SLT/etc which expected a float to
be returned. These were previously getting integer 0/-1 values.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: 10.2 <mesa-stable@lists.freedesktop.org>
2014-05-07 20:40:46 -04:00
Ilia Mirkin
5a40fe03f7 nv50/ir: allow load propagation when flags are defined
The old condition disallowed load propagation any time flags were
defined, even with e.g. set and a constbuf reference. The new condition
disallows it only with immediate propagation. (There are no opcodes that
set the condition flag and have an immediate argument.)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-07 20:40:46 -04:00