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Author SHA1 Message Date
David Rosca
c447c6fe17 egl/wayland: Fix flush after blit in swap buffers multi-GPU case 
dri2_wl_swap_buffers_with_damage is not used by swrast, so the swrast
condition there is wrong and instead it should always flush.

Fixes: fd17c018e9 ("egl/wayland: replace a couple DRI2_FLUSH checks with non-kms_swrast checks")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30964>
 2024-09-02 13:22:30 +00:00
Georg Lehmann
8f3bb1fb2e aco/ra: always reuse def register for literal copy 
Foz-DB Vega10:
Totals from 4056 (6.43% of 63053) affected shaders:
Instrs: 5540797 -> 5540760 (-0.00%); split: -0.00%, +0.00%
CodeSize: 29680912 -> 29680812 (-0.00%); split: -0.00%, +0.00%
SGPRs: 307808 -> 307680 (-0.04%)
Latency: 82483179 -> 82484437 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 45546645 -> 45547091 (+0.00%); split: -0.00%, +0.00%
SClause: 185641 -> 185648 (+0.00%); split: -0.00%, +0.01%
Copies: 642229 -> 642214 (-0.00%); split: -0.01%, +0.01%
SALU: 643132 -> 643107 (-0.00%); split: -0.01%, +0.01%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30932>
 2024-09-02 11:09:55 +00:00
Georg Lehmann
5fb54d1fde aco/ra: fix copying 64bit literal to sgprs 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30932>
 2024-09-02 11:09:55 +00:00
Georg Lehmann
364764356c aco/ra: use parallelcopy to copy literal instead of s_mov 
This can result in smaller code size.

Foz-DB Vega10:
Totals from 4745 (7.53% of 63053) affected shaders:
CodeSize: 33014176 -> 33007088 (-0.02%); split: -0.02%, +0.00%
Copies: 690055 -> 704738 (+2.13%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30932>
 2024-09-02 11:09:55 +00:00
Georg Lehmann
607cf5a8e9 aco/ra: unconditionally replace literal with sgpr when promoting to VOP3 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30932>
 2024-09-02 11:09:55 +00:00
Samuel Pitoiset
8873382703 radv: fix emitting DGC indirect draws with drawid/base_instance 
This fixes test_execute_indirect_state_vbo_offsets, a new vkd3d-proton
test.

The drawid/base_instance bits were cleared by mistake.

Fixes: e59a16bbb8 ("radv: use an indirect draw when IBO isn't updated as part of DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30971>
 2024-09-02 09:58:32 +00:00
Juan A. Suarez Romero
1536b7e9a8 v3d/v3dv: build simulator references conditionally 
Instead of checking on run time if simulator is available or not, do it
at build time.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30900>
 2024-09-02 09:34:10 +00:00
Juan A. Suarez Romero
bf37bd7e26 vc4: build simulator references conditionally 
Instead of checking on run time if simulator is available or not, do it
at build time.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30900>
 2024-09-02 09:34:10 +00:00
Samuel Pitoiset
e4e789ce10 radv: allow VK_EXT_legacy_vertex_attributes with DGC 
Dynamic vertex input state is supported with DGC but it wasn't at the
time this extension has been introduced.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30957>
 2024-09-02 09:09:07 +00:00
Collabora's Gfx CI Team
b32b15f0df Uprev Piglit to 93b4bd2e0aaab1c22ae3e1a23f9e057a8f7451b2 
a3826de3c2...93b4bd2e0a

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30863>
 2024-09-02 08:30:51 +00:00
Jose Maria Casanova Crespo
5fed6bee19 v3d: v3d_resource Use LINEAR layout for importing with INVALID modifier 
v3d_resource_from_handle when importing a DRM_FORMAT_MOD_INVALID
considered that if we had a render-only device the resource layout was
linear and if we didn't have render-only the resource layout was tiled.

This change honors the resource creation with the SCANOUT flag
independently of the availability of the render-only for the
DRM_FORMAT_MOD_INVALID modifier.

It also fixes most of the failing piglit text for:

spec@ext_image_dma_buf_import@ext_image_dma_buf_import.*

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11594
Cc: mesa-stable
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30946>
 2024-09-02 10:01:12 +02:00
Pavel Ondračka
9a213b882e r300/ci: add more flakes 
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30966>
 2024-09-01 17:34:43 +02:00
Juan A. Suarez Romero
86c5298cdf vc4/ci: update expected results 
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30965>
 2024-09-01 16:36:34 +02:00
Eric Engestrom
2d10233f2f ci: add virgl & venus to the s390 build 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30954>
 2024-08-31 18:55:15 +00:00
Georg Lehmann
b78a3d4de9 zink: switch to derivative intrinsics 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30941>
 2024-08-31 07:38:23 +00:00
Caio Oliveira
3f6b5ea27a intel/brw: Use linear walk when shader requires DERIVATIVE_GROUP_LINEAR 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30955>
 2024-08-30 20:24:42 +00:00
Mike Blumenkrantz
898012ba11 egl: use more precise conditional for passing fd through to dri screen create 
kms_swrast is included in the swrast conditional and needs a fd,
and there is a flag which indicates pure swrast which can be used to
ensure this case is detected

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30951>
 2024-08-30 18:42:27 +00:00
Samuel Pitoiset
45319cb253 radv: specialize push constant stages with DGC 
Even if the layout declares using push constant for more stages than
needed, upload_sgpr/inline_sgpr will prevent the DGC prepare shader to
emit them because it's initialized to 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30924>
 2024-08-30 18:02:23 +00:00
Samuel Pitoiset
8c5358040d radv: move emitting VBOs with DGC 
Only for graphics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30924>
 2024-08-30 18:02:22 +00:00
Samuel Pitoiset
2234e6d75a radv: add a helper to store data to the DGC upload space 
The offset is automatically incremented when something is stored.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30924>
 2024-08-30 18:02:22 +00:00
Samuel Pitoiset
330d6e0951 radv: stop passing the upload offset to dgc_emit_bind_pipeline() 
This doesn't do anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30924>
 2024-08-30 18:02:22 +00:00
Samuel Pitoiset
e96be348f2 radv: move emitting the compute pipeline with DGC 
Only compute is supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30924>
 2024-08-30 18:02:22 +00:00
Mike Blumenkrantz
ecb788624b revert part of 94e470a32d 
accidentally added during rebase

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30949>
 2024-08-30 17:08:33 +00:00
Louis-Francis Ratté-Boulianne
9d981a4c5b panfrost: properly lower DrawID sysval on v9 GPUs 
We only use special DrawID register on v10 GPUs so we still need to
lower to sysval on any earlier generation.

Fixes commit f390835074

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30933>
 2024-08-30 16:30:40 +00:00
Sai Teja
05f6e9f11e ci: Disable angle jobs for GL changes 
Mesa's GL stack changes doesn't affect angle in any
way for now. Thus, drop angle jobs for GL changes from
intel and amd CI.

Signed-off-by: Sai Teja <saiteja13427@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30943>
 2024-08-30 15:09:15 +00:00
Ali Homafar
3b581ed1f8 zink: Optimize descriptor buffers struct filling 
Improve buffer descriptor filling for UBOs and SSBOs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30390>
 2024-08-30 14:20:19 +00:00
Mike Blumenkrantz
94e470a32d zink: update profile with missing extensions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30944>
 2024-08-30 13:37:25 +00:00
Daniel Stone
2e97d7b35c doc/llvmpipe: Update URL to fix linkcheck 
linkcheck-docs has been failing for a little while now.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30939>
 2024-08-30 13:26:41 +00:00
Christian Gmeiner
42f5b99a34 etnaviv: Switch to etna_core_has_feature(..) for has_halti2_instructions 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
2978d10203 etnaviv: Switch to etna_core_has_feature(..) for npot_tex_any_wrap 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
61d0ec5aec etnaviv: Switch to stream_count from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
8b0a409431 etnaviv: Switch to max_registers from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
89e286892d etnaviv: Switch to num_constants from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
f34bf16114 etnaviv: npu: Drop not used spec values 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
92a6f697d5 etnaviv: npu: Switch to use etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
226e7d952f etnaviv: Switch to vertex_output_buffer_size from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
d5b4758417 etnaviv: Switch to vertex_cache_size from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
0a6baea787 etnaviv: Switch to shader_core_count from etna_core_info 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Christian Gmeiner
f304dc57ae etnaviv: Drop has_sin_cos_sqrt and has_sign_floor_ceil 
They are not read anywhere.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
 2024-08-30 12:45:58 +00:00
Jordan Justen
3e4f73b3a0 intel/dev: Update hwconfig => max_threads_per_psd for Xe2 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30887>
 2024-08-30 01:53:55 -07:00
Qiang Yu
588a65f29a ac: do not lower some ops in nir_lower_packing 
AMD does not implement nir_op_pack_32_4x8_split, others
are implemented, so don't lower them.

Fixes: 0f937426cc ("radeonsi: lower subgroup ops after wave size is known")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11781
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30885>
 2024-08-30 05:46:51 +00:00
Qiang Yu
d43c5003fc nir: add skip_lower_packing_ops shader compile option 
Drivers like radeonsi and radv prefer to not lowering
some packing ops.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30885>
 2024-08-30 05:46:51 +00:00
Eric Engestrom
6c1d0b82fb turnip/ci: add vkd3d job on the a750 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29845>
 2024-08-30 05:10:53 +00:00
Caio Oliveira
e4f090d3a6 intel/brw: Remove special treatment for 2-src in emit() helper 
For Gfx9+ no 2-src instructions need sources to fixed up.  Special
treatment remains for 3-src instructions.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30911>
 2024-08-30 04:33:47 +00:00
Ian Romanick
73f365e208 intel/brw: load_offset cannot be constant on this path 
Literally inside an if-statement (about 26 lines before this hunk)
that checks for !nir_src_is_const(instr->src[1]).

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00
Ian Romanick
fef175de09 intel/brw: Enable constant propagation for a couple more logical sends 
This prevents some regressions later in the MR. Once load_const
operations are marked as is_scalar, they will cesase to get the
automatic constant propagation that occurs in try_rebuild_source.

No shader-db or fossil-db changes on any Intel platform.

v2: Slightly relax source restrictions on
SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL. Add a comment
explaining the restriction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00
Ian Romanick
c6a8b382fd intel/brw: Relax is_partial_write check in cmod propagation 
The is_partial_write check is too strict because it tests two separate
things. It tests whether or not the instruction always writes a value
(i.e., is it predicated), and it tests whether or not the instruction
writes a complete register. This latter check is problematic as it
perevents cmod propagation in SIMD1, and it prevents cmod propagation in
SIMD8 when the destination size is 16 bits.

This check is unnecessary. Cmod propagation already checks that the
region written and region read overlap. It also already checks that the
execution sizes of the instructions match. Further restriction based on
the specific parts of the register written only generates false
negatives.

v2: Relax all of the calls to is_partial_write. Suggested by Caio.

No shader-db changes on any Intel platform.

fossil-db:

Meteor Lake
Totals:
Instrs: 151505520 -> 151502923 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17201385104 -> 17194901423 (-0.04%); split: -0.06%, +0.02%
Spill count: 80827 -> 80837 (+0.01%)
Fill count: 152693 -> 152692 (-0.00%); split: -0.01%, +0.01%

Totals from 346 (0.05% of 630198) affected shaders:
Instrs: 1257205 -> 1254608 (-0.21%); split: -0.21%, +0.00%
Cycle count: 5532845647 -> 5526361966 (-0.12%); split: -0.18%, +0.06%
Spill count: 32903 -> 32913 (+0.03%)
Fill count: 64338 -> 64337 (-0.00%); split: -0.03%, +0.03%

DG2
Totals:
Instrs: 151531440 -> 151528055 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17200238927 -> 17197996676 (-0.01%); split: -0.03%, +0.02%
Spill count: 81003 -> 80971 (-0.04%); split: -0.04%, +0.00%
Fill count: 152975 -> 152912 (-0.04%); split: -0.05%, +0.01%

Totals from 346 (0.05% of 630198) affected shaders:
Instrs: 1260363 -> 1256978 (-0.27%); split: -0.27%, +0.00%
Cycle count: 5532019670 -> 5529777419 (-0.04%); split: -0.09%, +0.05%
Spill count: 33046 -> 33014 (-0.10%); split: -0.11%, +0.01%
Fill count: 64581 -> 64518 (-0.10%); split: -0.13%, +0.03%

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
Totals:
Instrs: 149972324 -> 149972289 (-0.00%)
Cycle count: 15566495293 -> 15565151171 (-0.01%); split: -0.01%, +0.00%

Totals from 16 (0.00% of 629912) affected shaders:
Instrs: 351194 -> 351159 (-0.01%)
Cycle count: 3922227030 -> 3920882908 (-0.03%); split: -0.04%, +0.00%

Skylake
Totals:
Instrs: 140787999 -> 140787983 (-0.00%); split: -0.00%, +0.00%
Cycle count: 14665614947 -> 14665515855 (-0.00%); split: -0.00%, +0.00%
Spill count: 58500 -> 58501 (+0.00%)
Fill count: 102097 -> 102100 (+0.00%)

Totals from 16 (0.00% of 625685) affected shaders:
Instrs: 343560 -> 343544 (-0.00%); split: -0.01%, +0.01%
Cycle count: 3354997898 -> 3354898806 (-0.00%); split: -0.01%, +0.01%
Spill count: 16864 -> 16865 (+0.01%)
Fill count: 27479 -> 27482 (+0.01%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00
Ian Romanick
13332c236b intel/brw: Unconditionally run optimizations after nir_opt_uniform_subgroup 
I observed some ray tracing shaders where a resource_intel inside a
loop was non-uniform, and some code was lowered to account for
that. Eventually the loop containing the resource_intel was unrolled,
and the resource_intel became uniform.

For example, nir_opt_uniform_subgroup can transform something like

    con loop {
        con block b5:        // preds: b4 b8
        con 32    %330 = @read_first_invocation (%329)
        con 1     %331 = ieq %330, %329
                         // succs: b6 b7
        if %331 {
            con block b6:        // preds: b5
            con 32    %332 = iadd %120.b, %330
            con 32    %333 = @resource_intel (%125 (0xdeaddeed), %332, %125 (0xdeaddeed), %3 (0x0)) (desc_set=1, binding=2, resource_intel=bindless|non-uniform, resource_block_intel=-1)
            div 32x4  %334 = (float32)txl %333 (texture_handle), %130 (sampler_handle), %327 (coord), %275 (lod), 0 (texture), 0 (sampler)
                             break
                             // succs: b9
        } else {
            con block b7:  // preds: b5, succs: b8
        }
        con block b8:  // preds: b7, succs: b5
    }

into

    con loop {
        con block b5:        // preds: b4 b8
        con 1     %331 = ieq %329, %329
                         // succs: b6 b7
        if %331 {
            con block b6:        // preds: b5
            con 32    %332 = iadd %120.b, %329
            con 32    %333 = @resource_intel (%125 (0xdeaddeed), %332, %125 (0xdeaddeed), %3 (0x0)) (desc_set=1, binding=2, resource_intel=bindless|non-uniform, resource_block_intel=-1)
            div 32x4  %334 = (float32)txl %333 (texture_handle), %130 (sampler_handle), %327 (coord), %275 (lod), 0 (texture), 0 (sampler)
                             break
                             // succs: b9
        } else {
            con block b7:  // preds: b5, succs: b8
        }
        con block b8:  // preds: b7, succs: b5
    }

Notice that %331 is now a tautology. Running brw_nir_optimize again
eliminates the loop.

v2: Add a comment in the code explaining the rationale. Suggested by
Ken. Update the commit message. Suggested by Caio.

shader-db:

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19733448 -> 19733330 (<.01%)
instructions in affected programs: 14120 -> 14002 (-0.84%)
helped: 32 / HURT: 3

total cycles in shared programs: 916254496 -> 916226288 (<.01%)
cycles in affected programs: 2035116 -> 2006908 (-1.39%)
helped: 19 / HURT: 13

total spills in shared programs: 5807 -> 5807 (0.00%)
spills in affected programs: 26 -> 26 (0.00%)
helped: 1 / HURT: 1

total fills in shared programs: 6794 -> 6792 (-0.03%)
fills in affected programs: 84 -> 82 (-2.38%)
helped: 1 / HURT: 1

LOST:   1
GAINED: 1

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20393084 -> 20392971 (<.01%)
instructions in affected programs: 21750 -> 21637 (-0.52%)
helped: 31 / HURT: 4

total cycles in shared programs: 880273065 -> 880247818 (<.01%)
cycles in affected programs: 2546748 -> 2521501 (-0.99%)
helped: 18 / HURT: 9

total spills in shared programs: 4628 -> 4630 (0.04%)
spills in affected programs: 287 -> 289 (0.70%)
helped: 1 / HURT: 2

total fills in shared programs: 5381 -> 5376 (-0.09%)
fills in affected programs: 711 -> 706 (-0.70%)
helped: 2 / HURT: 2

LOST:   1
GAINED: 1

fossil-db:

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 151513669 -> 151505520 (-0.01%); split: -0.01%, +0.00%
Send messages: 7459339 -> 7459396 (+0.00%)
Loop count: 49111 -> 47588 (-3.10%)
Cycle count: 17208178205 -> 17201385104 (-0.04%); split: -0.05%, +0.01%
Spill count: 80830 -> 80827 (-0.00%); split: -0.02%, +0.01%
Fill count: 152754 -> 152693 (-0.04%); split: -0.04%, +0.00%
Scratch Memory Size: 4136960 -> 4130816 (-0.15%)
Max live registers: 32016493 -> 32015955 (-0.00%); split: -0.00%, +0.00%

Totals from 672 (0.11% of 630198) affected shaders:
Instrs: 1352428 -> 1344279 (-0.60%); split: -0.78%, +0.17%
Send messages: 54302 -> 54359 (+0.10%)
Loop count: 6124 -> 4601 (-24.87%)
Cycle count: 1260266379 -> 1253473278 (-0.54%); split: -0.69%, +0.16%
Spill count: 15967 -> 15964 (-0.02%); split: -0.09%, +0.08%
Fill count: 36245 -> 36184 (-0.17%); split: -0.18%, +0.01%
Scratch Memory Size: 740352 -> 734208 (-0.83%)
Max live registers: 50699 -> 50161 (-1.06%); split: -1.45%, +0.39%

Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown)
Totals:
Instrs: 149976046 -> 149971100 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 7685264 -> 7685256 (-0.00%)
Cycle count: 15566401168 -> 15566405478 (+0.00%); split: -0.00%, +0.00%
Spill count: 61238 -> 61240 (+0.00%)
Fill count: 107301 -> 107289 (-0.01%)
Max live registers: 31992969 -> 31993857 (+0.00%); split: -0.00%, +0.00%

Totals from 553 (0.09% of 629912) affected shaders:
Instrs: 557027 -> 552081 (-0.89%); split: -0.90%, +0.01%
Subgroup size: 8648 -> 8640 (-0.09%)
Cycle count: 150154496 -> 150158806 (+0.00%); split: -0.23%, +0.24%
Spill count: 181 -> 183 (+1.10%)
Fill count: 440 -> 428 (-2.73%)
Max live registers: 33698 -> 34586 (+2.64%); split: -0.02%, +2.65%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00
Ian Romanick
65eb7ed5fc intel/brw: Run intel_nir_lower_conversions only after brw_nir_optimize 
Without this, the next commit tiggers assertions.

v2: Unconditionally do the lowering after brw_nir_optimize. Suggested by
Caio.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00
Ian Romanick
572e00dd66 intel/brw: Copy prop from raw integer moves with mismatched types 
The specific pattern from the unit test was observed in ray tracing
trampoline shaders.

v2: Refactor the is_raw_move tests out to a utility function. Suggested
by Ken.

v3: Fix a regression caused by being too picky about source
modifiers. This was introduced somewhere between when I did initial
shader-db runs an v2.

v4: Fix typo in comment. Noticed by Caio.

shader-db:

All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19734086 -> 19733997 (<.01%)
instructions in affected programs: 135388 -> 135299 (-0.07%)
helped: 76 / HURT: 2

total cycles in shared programs: 916290451 -> 916264968 (<.01%)
cycles in affected programs: 41046002 -> 41020519 (-0.06%)
helped: 32 / HURT: 29

fossil-db:

Meteor Lake, DG2, and Skylake had similar results. (Meteor Lake shown)
Totals:
Instrs: 151531355 -> 151513669 (-0.01%); split: -0.01%, +0.00%
Cycle count: 17209372399 -> 17208178205 (-0.01%); split: -0.01%, +0.00%
Max live registers: 32016490 -> 32016493 (+0.00%)

Totals from 17361 (2.75% of 630198) affected shaders:
Instrs: 2642048 -> 2624362 (-0.67%); split: -0.67%, +0.00%
Cycle count: 79803066 -> 78608872 (-1.50%); split: -1.75%, +0.25%
Max live registers: 421668 -> 421671 (+0.00%)

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
Totals:
Instrs: 149995644 -> 149977326 (-0.01%); split: -0.01%, +0.00%
Cycle count: 15567293770 -> 15566524840 (-0.00%); split: -0.02%, +0.01%
Spill count: 61241 -> 61238 (-0.00%)
Fill count: 107304 -> 107301 (-0.00%)
Max live registers: 31993109 -> 31993112 (+0.00%)

Totals from 17813 (2.83% of 629912) affected shaders:
Instrs: 3738236 -> 3719918 (-0.49%); split: -0.49%, +0.00%
Cycle count: 4251157049 -> 4250388119 (-0.02%); split: -0.06%, +0.04%
Spill count: 28268 -> 28265 (-0.01%)
Fill count: 50377 -> 50374 (-0.01%)
Max live registers: 470648 -> 470651 (+0.00%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30251>
 2024-08-30 03:39:31 +00:00