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Author SHA1 Message Date
Danylo Piliaiev
5d151ddfba turnip: Disallow non-linear tiling when casting R8G8 to other fmts 
R8G8 have a different block width/height and height alignment from other
formats that would normally be compatible (like R16), and so if we are
trying to, for example, sample R16 as R8G8 we need to demote to linear.

Follows the fix in Freedreno: b97e3bb2e1

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15465>
 2022-03-22 13:47:21 +00:00
Danylo Piliaiev
a70b197741 turnip: Force linear mode for non-ubwc R8G8 formats 
Non-UBWC tiled R8G8 is probably buggy since media formats are always
either linear or UBWC. There is no simple test to reproduce the bug.
However it was observed in the wild leading to an unrecoverable hang
on a650/a660.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5926

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15465>
 2022-03-22 13:47:21 +00:00
shansheng.wang
1bd8ef0c89 frontends/va: fix coredump as creating surface with VAConfigAttrib 
As creating surface with VAConfigAttrib, checking if modifier from attrib list is null

Signed-off-by: shanshengwang <shansheng.wang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15483>
 2022-03-22 13:07:56 +00:00
Mike Blumenkrantz
f9390dac23 zink: use the current compute shader, not the base one 
this is the current variant and the one that should be used

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15501>
 2022-03-22 12:54:43 +00:00
Mike Blumenkrantz
d8d7ba8b5d zink: create compute pipeline after updating shader variants 
it turns out shader variants don't work if you generate them after you
determine which variant to use

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15501>
 2022-03-22 12:54:43 +00:00
Ganesh Belgur Ramachandra
582e7f1599 radeonsi: NIR equivalent of si_create_clear_buffer_rmw_cs() 
Replaced the existing internal TGSI compute shader, which clears
a read-modify-write buffer, with its NIR equivalent. The disassembly
shader generated by the new NIR variant is identical to the previous
implementation. These changes remove the additional conversion step
from TGSI to NIR for the shader at runtime. Tested on a Navi 23 card.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15356>
 2022-03-22 12:35:41 +00:00
Mihai Preda
ff2b2bc568 amd/ac_gpu_info: fix warning on fread unused result 
fixes this warning:
ignoring return value of 'fread' declared with attribute 'warn_unused_result' [-Wunused-result]

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15502>
 2022-03-22 11:50:37 +00:00
Kenneth Graunke
49dd707ca2 intel: Add INTEL_DEBUG=noccs alias for INTEL_DEBUG=norbc 
When CCS compression first came out on Skylake, we referred to it as
"renderbuffer compression", or RBC for short.  However, that name has
long since fallen out of favor, and we refer to it as CCS nearly
everywhere.

This patch renames DEBUG_NO_RBC to DEBUG_NO_CCS inside the codebase
for clarity, and adds INTEL_DEBUG=noccs.  The legacy INTEL_DEBUG=norbc
name continues to work, because it's one line of code and having both
names makes our lives easier in the interim.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15447>
 2022-03-22 06:23:10 +00:00
Kenneth Graunke
85d30846db nir: Print divergence status of SSA values if analysis was ever run. 
After running divergence analysis, we include "div" or "con" for each
SSA def's divergence/convergence status:

	vec1 32 div ssa_35 = fddy ssa_34
	vec1 32 con ssa_36 = fddy ssa_6.x

We omit this before the first time divergence analysis has been run.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15445>
 2022-03-21 22:46:34 -07:00
Mike Blumenkrantz
09a37ad046 zink: ci updates 
these should be properly disabled now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15500>
 2022-03-21 23:13:21 -04:00
Mike Blumenkrantz
2139ef8951 zink: ci updates 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 23:00:56 -04:00
Mike Blumenkrantz
5b77a17472 zink: use the right query type for primitives generated 
this should've always been clipping invocations, but I got scared because
then tests with rasterization_discard=1 fail and I didn't handle that instead

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 23:00:40 -04:00
Mike Blumenkrantz
9153fb7fbe zink: use EXT_color_write_enable to mask out primgen+rasterizer_discard output 
by disabling color and depth write, the side effects of force-disabling discard can
be mitigated

fixes:
KHR-GL46.tessellation_shader.single.isolines_tessellation
KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.data_pass_through
KHR-GL46.tessellation_shader.tessellation_invariance.invariance_rule3
KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification
KHR-GL46.tessellation_shader.tessellation_shader_quads_tessellation.degenerate_case
KHR-GL46.tessellation_shader.tessellation_shader_quads_tessellation.inner_tessellation_level_rounding
KHR-GL46.tessellation_shader.tessellation_shader_tessellation.gl_InvocationID_PatchVerticesIn_PrimitiveID
KHR-GL46.tessellation_shader.vertex.vertex_spacing

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 23:00:28 -04:00
Mike Blumenkrantz
3892c13381 zink: add an alternate path for EXT_color_write_enable usage 
for drivers where this is broken/missing, the same effect can be achieved
by feeding the renderpass a framebuffer with null/dummy attachments

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:12 -04:00
Mike Blumenkrantz
447099629e zink: use EXT_color_write_enable when possible 
this should only verify that drivers aren't completely broken by
enabling it and have no other changes

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:12 -04:00
Mike Blumenkrantz
ecca2564c1 zink: disable color_write_enable on ANV 
this breaks the driver

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:12 -04:00
Mike Blumenkrantz
49a20e0981 zink: start a unified driver workarounds struct 
eventually anything that checks driverID should be moved here for ease of
reference/updating

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:11 -04:00
Mike Blumenkrantz
0a80f94de0 zink: force disable rasterization discard if primgen query is active 
this query requires rasterization to pass the clipping invocations stage,
which means discard is impossible

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:11 -04:00
Mike Blumenkrantz
795925e0ff zink: hook up EXT_color_write_enable 
no functional changes

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15392>
 2022-03-21 22:58:11 -04:00
Qiang Yu
9401990e6f nir/linker: set varying from uniform as flat 
Flat varying can save some rasterization compute cost
and register needed by shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15341>
 2022-03-22 01:33:23 +00:00
Qiang Yu
aaf951c47f lima: enable nir lower_varying_from_uniform 
Mali GPU pass varying by memory, so enable this optimization.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15341>
 2022-03-22 01:33:23 +00:00
Qiang Yu
2617e6c028 nir/linker: disable varying from uniform lowering by default 
This fixes performance regression for Specviewperf/Energy
on AMD GPU. Other GPUs passing varying by memory may choose
to re-enable it as need.

Fixes: 2604625043 ("nir/linker: support uniform when optimizing varying")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15341>
 2022-03-22 01:33:23 +00:00
Alyssa Rosenzweig
b219e9a96e asahi: Port driver to macOS 12.x ABI 
There's lots of reshuffling required. Nothing "interesting", though.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
1c6e77bd04 asahi: Don't clobber clear colours 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
b3be6d5263 asahi: Handle flushes of depth-only rendering 
Not totally right but this should be a start.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
a0197c16bc asahi: Wire in u_transfer_helper 
We need it for emulating packed depth/stencil as separate depth/stencil
resources, populating separate_stencil for us as required.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
3cd2833549 asahi: Generate IOGPU attachments dynamically 
Take a pipe_framebuffer_state and go from there. We need some care to
handle separate stencil, but the logic is largely routine.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
5d58d5caaf asahi: Add separate_stencil, internal_format fields 
Currently unused, but will be set when u_transfer_helper is integrated
for emulating packed depth/stencil.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:30 +00:00
Alyssa Rosenzweig
2c23bb49ef asahi: Add size field to slices 
Needed to size attachments for the kernel... for some reason. We already
compute this; just save it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Alyssa Rosenzweig
f5ae88d36f asahi: Identify IOGPU_MISC data structure 
This will be elaborated upon soon.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Alyssa Rosenzweig
d5ee1eacf1 asahi: Add stencil buffer attachment type 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Alyssa Rosenzweig
50f9b4ceba asahi: Identify IOGPU Internal Pipelines structure 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Alyssa Rosenzweig
eb9da583d7 asahi: Identify aux framebuffer data structure 
Total guess at the name.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Alyssa Rosenzweig
535f1c1166 asahi: Identify IOGPU Clear Z/S structure 
Not sure on the details yet but identify and dump the data structure to start.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
 2022-03-22 00:19:29 +00:00
Yonggang Luo
d9c3601e29 util: trim trailing space for files src/util/**/* 
Using the following bash script doing that
```
cd src/util
find . -type f -print0 | xargs -0 -n1 sed -i 's/[ \t]*$//'
```

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15093>
 2022-03-21 17:57:15 +00:00
Nanley Chery
da82358a52 ci/anv: Changes from enabling 8/16bpp CCS more 
- Fixes in dEQP-VK.dynamic_rendering.suballocation.multisample_resolve.*
- Fails in dEQP-VK.drm_format_modifiers.export_import.*

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15420>
 2022-03-21 17:36:10 +00:00
Nanley Chery
e2f0c859c2 Revert "anv: Disable CCS_E for some 8/16bpp copies on TGL+" 
This reverts commit d68b2db89c.

With this change, no regressions have been observed with the
dEQP-VK.synchronization* test group. There are regressions with
dEQP-VK.drm_format_modifiers.export_import.*, but those have been
root-caused to be test issues (see 3575).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6125
Fixes: 57445adc89 ("anv: Re-enable CCS_E on TGL+")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15420>
 2022-03-21 17:36:10 +00:00
Dylan Baker
fe65c5671b gallium/opencl: set OCL_ICD_FILENAMES with devenv 
So that `meson devenv` also sets up OpenCL.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15471>
 2022-03-21 16:58:14 +00:00
Pavel Ondračka
19db6b760a r300: set PVS_LAST_VTX_SRC_INST properly to last input read 
From docs:
The PVS Instruction which uses the Input Vertex Memory for the last
time. This value is used to free up the Input Vertex Slots ASAP.
This field must be set to a valid instruction.

Right now it is set to the last instruction. When the last read is
inside a loop, set it on the outhermost ENDLOOP. This could in theory
help performance, but none of my usual benchmarks including GLmark,
Unigine Sanctuary or Lightsmark show any measurable performance difference.

Suggested in: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6045

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15252>
 2022-03-21 16:37:11 +00:00
Karol Herbst
43c3f4386b nir: fix nir_sweep for printf 
I hit a memory corruption trying to implement printf for Rusticl

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15474>
 2022-03-21 13:23:04 +00:00
Lionel Landwerlin
44555e7f2c ci: enable intel-clc on some platforms 
We'll have to figure out the cross compiling strategy, in particular
for Android. But as it stands we can't have the target & host llvm
packages installed at the same time so we can't really compile it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
beadd0cb24 ci: enable llvm on debian-release build 
Needed for intel-clc.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
57dd9c66bd ci: add clang/spirv-tools/llvm-spirv packages to fedora container 
Needed for intel-clc.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
9ca29c687b intel/clc: disable tool prior to Gfx12.5 platforms 
This tool is currently only aimed at Gfx version 12.5+ with
COMPUTE_WALKER. We could make it work on earlier platforms but they
require pushing gl_SubgroupInvocation and the CLC code is missing the
back-end compiler set-up bits for that.

v2: Commit description by Jason

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
c735c4ca85 intel/clc: specify supported extensions 
Having everything ever known to man is confusing our SPIRV parser.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
a29b1d5716 intel/clc: allow producing SPIRV files 
Useful to debug the parser.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
77e929a527 intel/clc: allow multiple CL files to be compiled together 
v2: use util_dynarray_append() (Jason)
    identation fixes (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Jason Ekstrand
c15bf88f01 intel: Add a little OpenCL C compiler binary 
v2: Fix up indentation (Marcin)
    s/gen/gfx/ (Marcin)
    Deal with fd closing in success/fail cases (Marin)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
b1e7ce84cc meson: try to find clang-cpp before going through each module 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00
Lionel Landwerlin
ec6e247a40 intel/fs: handle inline data on OpenCL style kernels 
This is for Gfx12.5 with the COMPUTE_WALKER::Inline Data payload. We
do this in a similar way to the compute kernels.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
 2022-03-21 11:26:44 +00:00