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Author SHA1 Message Date
Mike Blumenkrantz
4ad64552b8 zink: add a util function for optimizing TRANSFER_DST image barriers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21397>
 2023-02-24 05:27:31 +00:00
Mike Blumenkrantz
fa6e6545b1 zink: add some tracking for copy box regions 
this enables tracking per-miplevel pipe_boxes for copy operations that
can then be used to avoid emitting barriers for successive copy operations
without overlapping regions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21397>
 2023-02-24 05:27:31 +00:00
Mike Blumenkrantz
935184ca44 util/box: add intersection test functions for 1d/3d 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21397>
 2023-02-24 05:27:31 +00:00
Caio Oliveira
8f3d0141de anv, hasvk: Align workaround address to 32B 
Not necessary but, all things being equal, be consistent with Iris.

Now that intel_debug_write_identifiers() already add the padding,
there's no need to include extra "+ 8" to the offset.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
Caio Oliveira
a4a0417263 iris, crocus: Align workaround address to 32B 
The workaround address is used as a source for push constants when
there's no resource available, that address must be 32B aligned.

This fixes invalid address being used for buffers in
3DSTATE_CONSTANT_* packets.

Now that intel_debug_write_identifiers() already add the padding,
there's no need to include extra "+ 8" to the offset.

Thanks to Xiaoming Wang that contributed to find and fix this issue.

Fixes: 2a4c361b06 ("iris: add identifier BO")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
Caio Oliveira
ea0ec8c562 intel: Add extra zeros at the end of debug identifiers 
Add at least a full aligned uint64_t of zero padding at the end
to make the identifiers easier to spot.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
David Heidelberg
387d131f96 ci/llvmpipe: add flake timeout for rusticl program@execute@builtin@builtin-float-sincos-1.0 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21510>
 2023-02-24 04:37:49 +00:00
Sil Vilerino
9490633723 d3d12: Fix VP9 Decode - Checking 0xFF instead of 0x7F for invalid frame_ref[i].Index7Bits 
Fixes: c8e8ce8359 ("d3d12: Add VP9 Decode support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21507>
 2023-02-24 01:49:28 +00:00
Caio Oliveira
fb2a6248d2 hasvk: Update driver name in debug information 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21481>
 2023-02-24 00:41:09 +00:00
Bas Nieuwenhuizen
ed76833705 radv: Implement & expose VK_EXT_pipeline_library_group_handles. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Bas Nieuwenhuizen
d0f7587109 radv: Use group handles based on shader hashes. 
Should be stable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Bas Nieuwenhuizen
913de78731 radv: Use provided handles for switch cases in RT shaders. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Bas Nieuwenhuizen
430170702e radv: Hash group handles as part of RT pipeline key. 
So that we can start varying them  to avoid collisions while keeping
handles stable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Bas Nieuwenhuizen
9eb76ab638 radv: Add helper to hash stages. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Mike Blumenkrantz
211ed8745f zink: add debug marker tracing for qbo updates 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21425>
 2023-02-23 21:47:20 +00:00
Mike Blumenkrantz
26aedae568 zink: add ZINK_DEBUG=map 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21425>
 2023-02-23 21:47:20 +00:00
Mike Blumenkrantz
03610a5aab zink: actually hook up ZINK_DEBUG=norp 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21425>
 2023-02-23 21:47:20 +00:00
Rob Clark
9e8450b65c freedreno/crashdec: Disable GALLIUM_DUMP_CPU 
We don't want util_cpu to vomit cpu caps all over the test output.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
3f227957d6 freedreno/crashdec: Handle multi-IB prefetching 
Add helper to scan the CP_INDIRECT_BUFFERs, and then work backwards
accounting for data buffered via ROQ prefetch to deduce the actual
SQE position at the time of the crash.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
ddc4e87438 freedreno/crashdec: Add another prefetch test 
Constructed with an invalid packet (0xdeadd00d) so there is no ambiguity
in the crash location.

This is expected to fail until the next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
643ee85103 freedreno/crashdec: Refactor crashdec tests 
Simplify the process of adding additional tests.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
7417432a28 freedreno/crashdec: Add prefetch test 
Add a crash where this was seen "in the wild" on a CTS test in
!17943 which requires handling multi-IB prefetching to correctly
location the crash location.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
9ececfc6e6 freedreno/cffdec: Fix hang location detection 
We were previously checking only every 8 dwords within the packet.  We
should instead just check if the hang location comes within the packet.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
924f264081 freedreno/cffdec: Add helper to parse CP_INDIRECT_BUFFER 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
c01ac4b583 freedreno/cffdec: Add helper to find next pkt 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Rob Clark
cb13e24758 freedreno/cffdec: Fix unitialized count for pkt2 
This was causing us to use the size of the previous packet.  Which just
happened to land on a valid packet because pkt2 only followed a
CP_INDIRECT_BUFFER.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
4060cf5772 freedreno/crashdec: Fix apparent off-by-one with ROQ size 
I have multiple examples where this register is too large by one
when comparing to the ROQ read/write pointers in CP_ROQ_*_STAT and the
ROQ data itself, as if it includes the dword most recently read too. I
have an example where it's off by 2 compared to the read pointer, but
the read pointer is also off by 1 itself judging by the SQE program
counter, so that may just be them not getting synchronized. This
off-by-one was getting in the way of figuring out exactly IB2 was being
processed in the next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
ce7225c0f9 freedreno/a6xx: Fill in ROQ status registers 
We had a bunch of registers only defined for some parts of ROQ but now
that we know the pattern for ROQ-related registers it's easy to fill in
the rest.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
44054b1f3b freedreno/a6xx: Fix CP_ROQ_THRESHOLDS_1 
Just by adding the ROQ_*_STAT registers following the previous pattern
it becomes obvious what these fields actually are.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
aba8aea2be freedreno/a6xx: Add CP_ROQ_*_STAT 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Connor Abbott
8c6d741e26 freedreno/a6xx: Rename CP_CSQ_IB*_STAT 
These don't correspond to the a3xx *_STAT registers, which we're about
to add so we need to rename them. The closest analogue is CP_CSQ_AVAIL,
although the sense is inverted (and we're not sure what the low 16 bits
are about). Also, the a3xx distinction between CSQ and STQ doesn't exist
anymore so don't use these outdated terms.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19551>
 2023-02-23 20:02:26 +00:00
Tapani Pälli
880a3efe6c anv: implement emission of 3DSTATE_HS for Wa_1306463417 
We need to emit 3DSTATE_HS for each primitive with tessellation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli
f8a1100ca1 anv: limit generated draws to pipelines without HS stage 
This is done for gfx11 specific workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli
2028f1caa3 anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state 
Patch packs 3DSTATE_HS state during pipeline creation but it
gets emitted only before 3DPRIMITIVE. We will later need this
to implement a workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli
a043ae8e24 iris: implement emission of 3DSTATE_HS for Wa_1306463417 
We need to emit 3DSTATE_HS for each primitive with tessellation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Mark Collins
e4ebb541c5 meson: update flex/bison requirement to cover all usages 
Meson silently drops outputs such as libvulkan-freedreno when
dependencies on flex/bison can't be satisfied rather than providing
an error which this commit fixes.

Signed-off-by: Mark Collins <mark@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21488>
 2023-02-23 19:00:19 +00:00
Eric Engestrom
61f45a6f44 gbm: drop unnecessary vulkan dependency 
gbm doesn't actually include vulkan headers

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21489>
 2023-02-23 18:31:22 +00:00
Eric Engestrom
2bf24c84f3 glx: include directly the useful vulkan header, instead of including everything 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21489>
 2023-02-23 18:31:22 +00:00
Eric Engestrom
c8d7e0c023 egl: include directly the useful vulkan header, instead of including everything 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21489>
 2023-02-23 18:31:22 +00:00
Chia-I Wu
e97ed4fc89 anv: process utrace payloads on queue submission 
anv_QueuePresentKHR is not called by apps that do not use WSI.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21456>
 2023-02-23 18:06:16 +00:00
Karmjit Mahil
aa791961a8 pvr: Add support for dynamic buffers descriptors 
This is based on the new approach of having a descriptor set
addresses table in memory. To handle dynamic offsets provided on
vkCmdBindDescriptorSets() we duplicate the set with dynamic
descriptors, apply the offsets, and write the new bo's address
into the table. There are better ways of handling dynamic
descriptors but this implementation won't require many/if any
changes in the compiler code.

The descriptor set itself doesn't allocate and reserve space for
the dynamic descriptors since they would all be collected together
when creating the pipeline layout. While copying the descriptor
set we allocate extra space at the end for the dynamic primaries
and secondaries to account for that.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21391>
 2023-02-23 16:26:51 +00:00
Väinö Mäkelä
2bef26ed04 ci/intel: Update hasvk HSW xfails 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:14 +00:00
Väinö Mäkelä
d6d8edf9ae hasvk: Handle subpass self-dependencies for stencil shadow copies 
Always copying when dstAccessMask includes texture operations is not
optimal, but it's good enough.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Väinö Mäkelä
d3162f97b5 hasvk: Mark VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL as stencil write optimal 
VK_KHR_synchronization2 added VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL, which
was not previously recognized by vk_image_layout_stencil_write_optimal.

Would close https://gitlab.freedesktop.org/mesa/mesa/-/issues/5578 if it
wasn't already closed.

Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Väinö Mäkelä
79a58cb79b hasvk: Enable PixelShaderKillsPixel when omask is used 
From the Haswell PRM Vol. 2b, 3DSTATE_WM::Pixel Shader Kill Pixel:
    "This bit is required to be ENABLED in the following situations:
     - The API pixel shader program contains "killpix" or "discard"
       instructions, or other code in the pixel shader kernel that can
       cause the final pixel mask to differ from the pixel mask received
       on dispatch.
     - A sampler with chroma key enabled with kill pixel mode is used by
       the pixel shader.
     - Any render target has Alpha Test Enable or AlphaToCoverage Enable
       enabled.
     - The pixel shader kernel generates and outputs oMask."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Mike Blumenkrantz
15b302179a aux/tc: add a 'has_resolve' member to tc_renderpass_info 
this indicates that the first color buffer gets resolved

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21365>
 2023-02-23 15:33:47 +00:00
Lionel Landwerlin
ce68824bdf anv: fix invalid masking of 48bit address 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4d05be49c2 ("anv: implement vkCmdTraceRaysIndirect2KHR")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21486>
 2023-02-23 15:02:45 +00:00
José Roberto de Souza
af994570f0 intel/blorp: Allocate only necessary amount of VERTEX_BUFFER_STATE 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
José Roberto de Souza
a364f23a6c intel: Make gen12 URB space reservation dependent on compute engine presence 
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
Karmjit Mahil
63278778c6 pvr: Add push consts support to descriptor program. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21387>
 2023-02-23 10:14:17 +00:00