Commit Graph

51 Commits

Author SHA1 Message Date
Eric Anholt
49d402e275 Merge remote branch 'origin/mesa_7_6_branch'
Conflicts:
	src/mesa/drivers/dri/intel/intel_fbo.c
	src/mesa/drivers/dri/intel/intel_mipmap_tree.c
	src/mesa/drivers/dri/intel/intel_mipmap_tree.h
	src/mesa/drivers/dri/intel/intel_tex_copy.c
	src/mesa/drivers/dri/intel/intel_tex_image.c
2009-10-23 15:21:05 -07:00
Eric Anholt
2d17dbfb53 intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.

Fixes piglit fbo-clearmipmap.

Bug #23552. (automatic mipmap generation)
2009-10-23 14:12:24 -07:00
Eric Anholt
3d78a86cd7 intel: Remove an unexplained flush from intelClearWithBlit. 2009-10-02 11:38:36 -07:00
Brian Paul
e61215242b intel: #include clean-ups 2009-09-08 14:33:47 -06:00
Eric Anholt
2d5c74fac3 intel: Add support for GL_ARB_map_buffer_range.
Passes glean's bufferObject test, and should provide good performance in the
cases applications are expected to use.
2009-08-28 15:29:35 -07:00
Eric Anholt
b82abaabee intel: Add some more safety asserts in the blit code. 2009-08-07 18:33:08 -07:00
Eric Anholt
3927874d9c intel: Make LOCK_HARDWARE recursive to avoid hand-rolling recursiveness. 2009-06-29 10:33:50 -07:00
Eric Anholt
1593a1bb34 intel: Bail on blits with non-tile-aligned offsets. 2009-06-23 19:31:12 -07:00
Eric Anholt
8f81a6468f intel: Avoid trying to do blits to Y tiled regions.
This is somewhat nasty, but we need to do Y-tiled depth for FBO support.
May help with corruption and hangs since enabling texture tiling, and
since switching depth textures to Y tiled.

Fixes piglit depthtex.c on 965.
2009-06-23 19:31:11 -07:00
Eric Anholt
6a49473ab5 intel: Remove long-unused intel_region_fill and intelEmitFillBlit. 2009-06-23 19:31:10 -07:00
Eric Anholt
2c30fd84df intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.
Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
2009-04-16 12:04:30 -07:00
Roland Scheidegger
fd83289dbf fix various small intel blitter issues
use color format constants instead of magic numbers
remove handling of cpp 0 or 3 (neither is possible) in various places
don't misconfigure 8 bit surface blits as rgb565
2009-03-28 01:53:59 +01:00
Eric Anholt
19e134051c intel: Fix bpp setting of blits to 8bpp targets.
This was causing hangs in cairogears, as we would blit to the 8bpp target
(A8 texture) as 16bpp, and stomp over state objects.
2009-03-05 23:43:43 -08:00
Eric Anholt
f085147258 intel: Remove a gratuitous MI_FLUSH after clearing with a blit.
The 3D destination shares the same cache so we don't have any trouble with
the later commands needing the writes flushed inside of the same batchbuffer.
2009-03-05 19:42:16 -08:00
Owain G. Ainsworth
b5da7feee0 Remove intel pageflipping support in its entirety.
It's been broken and deprecated for a while, so it's time to die. This has the
wonderful benefit of cleaning up the code a fair amount; making it marginally
less twisty.

I'm unsure if the for loops in IntelWindowMoved are still needed.
2009-01-20 11:52:32 -05:00
Pierre Willenbrock
a0d5c3cfe6 intel: Require the right amount of space in glBitmap blit acceleration.
This leads to problems when the batchbuffer is flushed, but the bitmap
data could not fit into it.
2008-12-08 14:06:51 -08:00
Eric Anholt
3e0164aabb i965: Add support for accelerated CopyTexSubImage.
There were hacks in EmitCopyBlit before to adjust offsets so that y=0 after
the offsets had been adjusted for a negative pitch.  It appears that those
hacks were due to an unclear and surprising aspect of the hardware: inverting
the pitch results in the blit into the specified rectangle being inverted,
without the user needing to adjust y and base offset.

Tested with piglit copytexsubimage test on 915GM and GM965.  Should fix
serious performance issues with ETQW and other applications.
2008-11-21 17:35:33 +08:00
Eric Anholt
0cade4de4f intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time.  Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
2008-10-28 13:23:33 -07:00
Xiang, Haihao
2a877411db intel: GL_FALSE on a BO if it won't be modified when mapping this BO. (thanks Eric). 2008-10-26 06:38:27 +08:00
Xiang, Haihao
f657c81911 intel: fallback for intelEmitCopyBlit.
Use _mesa_copy_rect instead of BLT operation if dri_bufmgr_check_aperture_space
still fails after flushing batchbuffer. Partial fix for #17964.
2008-10-24 15:55:32 +08:00
Brian Paul
ecadb51bbc mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template 2008-09-18 15:17:05 -06:00
Eric Anholt
35fd72756a intel: track move of bo_exec from drivers to bufmgr. 2008-09-10 13:59:45 -07:00
Dave Airlie
f75843a517 Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c.
2008-08-24 17:59:10 +10:00
Dave Airlie
7c81124d7c Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-24 17:52:40 +10:00
Eric Anholt
d2796939f1 intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff.  We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
2008-08-08 14:00:43 -07:00
Ian Romanick
1e645b3659 Merge branch 'master' into drm-gem
Conflicts:

	src/mesa/drivers/dri/common/dri_bufmgr.c
	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-25 18:31:44 -07:00
Eric Anholt
2e841880cf drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. 2008-07-11 18:58:19 -07:00
Dave Airlie
b52398571b intel: fix batch flushing problem with cliprects handling.
pointed out and debugged by stringfellow on #dri-devel
2008-07-11 07:28:55 +10:00
Eric Anholt
93f701bc36 intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.
Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup.  Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH.  Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
2008-06-26 15:29:28 -07:00
Eric Anholt
f6abe8f0f2 Merge commit 'origin/master' into drm-gem 2008-06-24 14:08:08 -07:00
Eric Anholt
eda68cccc0 i915: Add support for accelerated glBitmap, shared from 965. 2008-06-24 10:26:57 -07:00
Eric Anholt
654258a4fe Merge commit 'origin/master' into drm-gem 2008-06-18 14:07:38 -07:00
Eric Anholt
cf29ab3ba0 i915: Bug #14313: Fix accelerated (PBO) ReadPixels.
Refactoring of mine in 02d5ba8491 broke it
by failing to understand that the masking was about sign extension.
2008-06-18 13:50:49 -07:00
Eric Anholt
407ce3da3c [intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
2008-06-11 14:44:48 -07:00
Keith Packard
924eaa2f95 [intel] all flushing in intelEmitCopyBlit
Add both MI_FLUSH and intel_batchbuffer_flush to intelEmitCopyBlit.
This ensures that the data are flushed *and* the gem kernel driver sees the
various memory domain transitions.
2008-05-26 00:19:20 -07:00
Eric Anholt
a74bf4ef34 Emit a flush after the swapbuffers blit, so contents end up on the screen.
Otherwise, since the MI_FLUSH at the end of every batch had been removed,
non-automatic-flushing chips (965) wouldn't get flushed and apps with static
rendering would get partial screen contents until the server's blockhandler
flush kicked in.
2008-05-23 12:18:50 -07:00
Eric Anholt
ab50ddaa91 GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need.  Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
2008-05-07 13:51:29 -07:00
Eric Anholt
eb10cdc838 [intel] Fix build for GEM. TTM is now disabled, and fencing is gone.
Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish.  glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them.  The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
2008-05-02 14:11:19 -07:00
Dave Airlie
008653ac55 i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.

There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
2008-04-18 11:57:38 +10:00
Dave Airlie
7cc7ff7051 intel/fake_bufmgr: Attempt to restrict references to objects in a batchbuffer > aperture size.
So with compiz on Intel hw with fake bufmgr, opening 4 firefox windows at 1680x1050 and hitting alt-tab, could cause the batchbuffer to try and reference more than the 32MB of RAM allocated.

Fix 1:
Fix 1 is to pre-verify the list of buffers against the current batchbuffer and if it can't possibly fit in the aperture to flush the batchbuffer to the hardware
and try again. If the buffers still can't fit well then you are hosed as I'm not sure there is a nice way to tell anyone.

Fix 2:
Next problem was that even with a simple check for total < aperture, we ran
into fragmentation issues, this meant that half way down a set of buffers,
we would fail as no blocks were available. Fix this by nuking the memory
manager from orbit and letting it start again and relayout the blocks in a
manner that fits.

Fix 3:
Finally the initial problem we were seeing was a memcpy to a NULL backing store.
We seem to end up with a texture at some point that never gets mapped but ends up with data in it. compiz al-tab icons have this property. So I created a card dirty bit that memcpy's any buffer that is !static and is written to back to memory. This probably is wrong but it makes compiz work for now.

Caveats:
965 support is still fail.
2008-04-16 16:22:05 +10:00
Kristian Høgsberg
c5c73c1b60 Hook up i915 driver to new DRI2 infrastructure. 2008-02-14 17:56:44 -05:00
Eric Anholt
a04b632350 [intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:

- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
  (copybuffers, clears).

All callers should now be fixed to use one of these states for any batchbuffer
emits.  Thanks to Keith Whitwell for pointing out the failure.
2008-01-10 12:34:08 -08:00
Kristian Høgsberg
33c42c1262 [intel] Prepare intelCopyBuffer() for private back buffers. 2008-01-09 20:43:18 -05:00
Brian
601a6b872c Replace gl_framebuffer's _ColorDrawBufferMask with _ColorDrawBufferIndexes
Each array element is now a BUFFER_x token rather than a BUFFER_BIT_x bitmask.
The number of active color buffers is specified by _NumColorDrawBuffers.
This builds on the previous DrawBuffer changes and will help with drivers
implementing GL_ARB_draw_buffers.
2008-01-06 18:07:26 -07:00
Eric Anholt
bea6b5fe5a [965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
2007-12-20 11:32:55 -08:00
Eric Anholt
33487c15ba [intel] Improve INTEL_DEBUG=blit description of clearing. 2007-12-17 16:57:59 -08:00
Eric Anholt
c1d6b874b3 [intel] Cleanup of */intel_blit.c to bring the two closer. 2007-12-17 13:19:33 -08:00
Eric Anholt
7c71ef3a3d [intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes.  It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965).  The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-12 11:52:10 -08:00
Michel Dänzer
63e6bfe8db i915: Some additional blit fixes and assertions. 2007-11-26 17:35:35 +01:00
Eric Anholt
f00a64999c [intel] Add 965 support to shared intel_blit.c
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16 17:29:30 -08:00