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Author SHA1 Message Date
Jordan Justen
47aff2759f intel/pci_ids: Update ATS-M device names 
Ref: bspec 44477
Ref: https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/flex-series/products.html
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18303>
(cherry picked from commit 9283ffec14)
 2022-09-14 20:55:14 -07:00
pal1000
49fdd260a2 meson: Only draw with llvm depends on native directly 
Tests, softpipe or AMD drivers don't depend on it directly

Fixes: 3955dd07 ("meson/gallium: Add an option to not use LLVM for gallium draw module")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6817

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17675>
(cherry picked from commit f23dbcd642)
 2022-09-14 20:55:13 -07:00
Mike Blumenkrantz
0b081167b2 zink: don't emit illegal interpolation 
this is not valid for vertex inputs or fragment outputs

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18365>
(cherry picked from commit da1a3ed2ea)
 2022-09-14 20:55:12 -07:00
Mike Blumenkrantz
c3cccad441 zink: only add srgb mutable for images with modifiers 
these are supposed to be for dmabuf handling, so checking for mutable
swapchain is both pointless and wrong

Fixes: 28ee911ad6 ("zink: handle mutable swapchain images with dmabuf")

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>
(cherry picked from commit cd00a36d47)
 2022-09-14 20:55:12 -07:00
Mike Blumenkrantz
b5917e15f7 zink: explicitly use unsigned types for bit shifts 
fixes some ubsan errors

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>
(cherry picked from commit d9b8f8d46c)
 2022-09-14 15:43:46 -07:00
Emma Anholt
de8ec9b17a spirv: Mark phis as mediump instead of directly lowering them to 16 bit. 
This reverts commit 6f25d45877, replacing it
with GLSL_PRECISION_MEDIUM.  The previous commit ended up not being the
right approach, as it affected only nir vars for spirv phis and not other
nir vars, and we want a tool that does both.  The new
nir_lower_mediump_vars pass can do that for you.

No fossil-db change for my angle fossils run on radv.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>
(cherry picked from commit e1588cdf9e)
 2022-09-14 15:43:46 -07:00
Mike Blumenkrantz
9b94b96829 zink: check the variable mode before taking samplemask path in ntv 
this otherwise may break for function temps

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18375>
(cherry picked from commit 8abbc6b19b)
 2022-09-14 15:43:45 -07:00
Mike Blumenkrantz
9d0016594b zink: don't emit entrypoints for function temp variables 
UNASSIGNED-CoreValidation-Shader-InconsistentSpirv(ERROR / SPEC): msgNum: 7060244 - Validation Error: [ UNASSIGNED-CoreValidation-Shader-InconsistentSpirv ] Object 0: handle = 0x3c8a1d0, type = VK_OBJECT_TYPE_DEVICE; | MessageID = 0x6bbb14 | SPIR-V module not valid: OpEntryPoint interfaces should only list global variables

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18375>
(cherry picked from commit e2773d67fe)
 2022-09-14 15:43:45 -07:00
Connor Abbott
7cd4905eaf tu/lrz: Fix multiple depth attachment case with secondaries 
This is a counterpart to the previous commit. When we have multiple
depth attachments, in the secondary we currently don't disable LRZ and
so we may need a valid LRZ fast-clear base.

Fixes: 4b5f0d98 ("tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18369>
(cherry picked from commit f640661e54)
 2022-09-14 15:43:44 -07:00
Connor Abbott
7f79b1a010 tu/lrz: Fix multiple subpass case with secondaries 
In
dEQP-VK.renderpass.dedicated_allocation.attachment_allocation.input_output.94
we have the following:

- There is more than one subpass, but only one depth attachment.
- The first subpass doesn't use depth.
- The subpass that does use depth has a draw call in a secondary.

We wouldn't hit the case where there's more than one depth attachment,
but because tu_begin_resumed_renderpass() only looked at the first
subpass it wouldn't find the depth attachment and would leave LRZ
invalid and thus a NULL LRZ fast-clear base. Then
tu_begin_secondary_cmdbuf() would leave LRZ enabled and the draw would
have LRZ enabled, leading to a hang.

Fix this by making tu_begin_resumed_renderpass() match
tu_begin_renderpass() with how it finds the depth attachment.

Fixes: 4b5f0d98 ("tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18369>
(cherry picked from commit bf09a5881b)
 2022-09-14 15:43:44 -07:00
Samuel Pitoiset
d4c4412629 radv: fix bogus assertion with RADV_FORCE_VRS 
It supports VS, TES and GS.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18345>
(cherry picked from commit 047738daa7)
 2022-09-14 15:43:43 -07:00
Timur Kristóf
46d66bcb6f aco: Fix p_init_scratch for task shaders. 
Fixes: d2d94b62f2
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18339>
(cherry picked from commit 16c14663e5)
 2022-09-14 15:43:43 -07:00
Gert Wollny
c559159b71 r600/sfn: override register ID when it doesn't matter 
When a vec4 register only uses constant value of ignore
swizzles then emit zero as register ID.

Optimizing the register use in instructions that support this type
of swizzle may lead to the situation that the RA doesn't see the
register ID, because it is actually irreleant, in this case return
zero as register ID to avoid that the assembler uselessly reports
a high requirement for registers based on a stale register ID.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18343>
(cherry picked from commit ed294e0863)
 2022-09-14 15:43:42 -07:00
Dave Airlie
c9d05409ae llvmpipe: finish rendering before flushing frontbuffer resources. 
Fixes misrendering on front with mesa demos

Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18360>
(cherry picked from commit 91dcadf956)
 2022-09-14 15:43:42 -07:00
Alyssa Rosenzweig
726e9bbf60 pan/mdg: Print 3 sources for CSEL 
The third source exists logically but not architecturally. We still need to
print it. Caught by the assertion.

Fixes: 0ee24c46e0 ("pan/mdg: Only print 2 sources for ALU")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18338>
(cherry picked from commit 6fed616187)
 2022-09-14 15:43:41 -07:00
Gert Wollny
ee37cceabd virgl: when reading back wait first, then do the transfer 
Otherwise the transfer from the host might not be finished
when we try to read the data.

v2: always wait before readback, but also keep the wait after
  a possible readback, Itherwise TF fails in the CI.

Fixes: e87186fc67
    virgl: add virgl_resource_transfer_prepare

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18243>
(cherry picked from commit 6e2b01e5b8)
 2022-09-14 15:43:40 -07:00
Yiwei Zhang
086b44101c venus: allow no external memory handle when renderers lacks support 
This is to make vtest happy.

Fixes: 9c5a7ffbd8 ("venus: fix external memory ext filtering")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18331>
(cherry picked from commit 0e0e5d1f20)
 2022-09-14 15:11:39 -07:00
Kenneth Graunke
a00e1b3a63 crocus: Fix memory leaks on iris_resource_create failure paths 
We've already allocated the pipe resource, so we ought to free it
before returning.

Fixes: d8a38edc48 ("crocus: fail resource allocation properly.")
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18311>
(cherry picked from commit 6c7916b7f6)
 2022-09-14 15:11:38 -07:00
Kenneth Graunke
51cd3f89a1 iris: Delete unused iris_screen::aperture_bytes field 
This was effectively removed in bb3545a6, but the field wasn't deleted,
leaving it there to troll people.  screen->aperture_bytes is 0?  What?

Fixes: bb3545a6ee ("intel: Store the aperture size in devinfo.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Mark Janes markjanes@swizzler.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18311>
(cherry picked from commit 6a1f7e623f)
 2022-09-14 15:11:38 -07:00
Pierre-Eric Pelloux-Prayer
84ef8f31f6 radeonsi: use nir_opt_large_constants earlier 
Calling it before nir_convert_to_lcssa helps in some cases,
because the NIR is simpler and nir_opt_large_constants can
detect that a variable is constant.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7059
CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18147>
(cherry picked from commit df2eaba411)
 2022-09-14 15:11:38 -07:00
Karol Herbst
3632392123 nouveau/mm: make code thread safe 
With this helgrind doesn't report any races in this code.

Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10752>
(cherry picked from commit 35d28251d1)
 2022-09-14 15:11:38 -07:00
Karol Herbst
b4c8e01393 nouveau: use the contexts pushbuf and client where possible 
At the moment the context uses the screens object, but in order to fix
threading without having to lock too much we will have to allocate those
objects per context later.

Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10752>
(cherry picked from commit 607a9e1fd2)
 2022-09-14 15:11:38 -07:00
Rhys Perry
02a7e1b33c aco: add SCC clobber in build_cube_select 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17991>
(cherry picked from commit 290df95870)
 2022-09-14 15:08:47 -07:00
Mike Blumenkrantz
80c165d155 zink: don't call util_queue_fence_init in zink_screen_get_pipeline_cache() 
this might accidentally clobber existing jobs

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18197>
(cherry picked from commit 40878e212f)
 2022-09-14 15:08:44 -07:00
Marcin Ślusarz
3b11e41489 anv: disable task redistribution 
If task redistribution is enabled, then some mesh shaders read
garbage from task payload.

It may be a hardware bug, or it may be our bug. Who knows :(

This change will probably negatively affect performance of task
shader-enabled workloads on multi-slice GPUs, because mesh shaders
will be executed only on the slice where task shader was spawned.

Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16197>
(cherry picked from commit 4eaecd7965)
 2022-09-14 15:08:38 -07:00
Chia-I Wu
6a936dc090 ir3: fix predicate splitting in scheduler 
Fix up src->def->instr, not src->instr.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7014
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18096>
(cherry picked from commit b1cb764316)
 2022-09-14 15:08:24 -07:00
Rhys Perry
0e9cbac188 aco: don't expand vec3 VS input load to vec4 on GFX6 
Removes the (small) possibility of invalid memory access.

fossil-db (pitcairn):
Totals from 35456 (26.15% of 135610) affected shaders:
MaxWaves: 259508 -> 260642 (+0.44%); split: +0.44%, -0.01%
Instrs: 7915383 -> 7965774 (+0.64%); split: -0.09%, +0.72%
CodeSize: 37163748 -> 37524804 (+0.97%); split: -0.04%, +1.01%
SGPRs: 1515128 -> 1513576 (-0.10%); split: -0.27%, +0.17%
VGPRs: 1218376 -> 1211160 (-0.59%); split: -0.71%, +0.12%
SpillSGPRs: 1152 -> 1144 (-0.69%)
Latency: 83777626 -> 83867137 (+0.11%); split: -0.61%, +0.72%
InvThroughput: 25722445 -> 25727745 (+0.02%); split: -0.23%, +0.25%
VClause: 232058 -> 230464 (-0.69%); split: -2.53%, +1.84%
SClause: 322579 -> 322108 (-0.15%); split: -0.76%, +0.61%
Copies: 547032 -> 547954 (+0.17%); split: -1.83%, +2.00%
Branches: 72538 -> 72542 (+0.01%)
PreVGPRs: 898453 -> 897584 (-0.10%); split: -0.13%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 030d6f873e)
 2022-09-14 15:08:23 -07:00
Rhys Perry
064abf28b6 aco: fix 16-bit VS inputs 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 3fba5bb9cc ("aco: implement 16-bit vertex fetches with tbuffer_load_format_d16_*")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 3260844448)
 2022-09-14 15:08:22 -07:00
Rhys Perry
3f3ecdccb1 radv: fix 16-bit support in radv_lower_vs_input 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091 ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 9ae13a9bd3)
 2022-09-14 15:08:22 -07:00
Rhys Perry
70dcad3214 radv: remove claimed support for sRGB vertex buffer formats 
These probably don't work.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 82f9e40851)
 2022-09-14 15:08:21 -07:00
Samuel Pitoiset
8abdd60d1f radv: re-emit viewports if negative one to one or depth clamp mode changed 
The following sequence would be broken if we don't re-emit viewports.

vkCmdSetViewport()
VkCmdBindPipeline(negative_one_to_one = false)
vkCmdDraw()
VkCmdBindPipeline(negative_one_to_one = true)
vkCmdDraw()

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18245>
(cherry picked from commit 64045fcf7c)
 2022-09-14 15:08:21 -07:00
Erik Faye-Lund
88a188cc39 zink: wrap discard in a function 
This makes discard less weird, and allows us to treat it as
control-flow. This makes things less bizarre for drivers.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7070
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
(cherry picked from commit b7601dd27e)
 2022-09-14 14:37:01 -07:00
Erik Faye-Lund
ccac10eb5a zink: add spirv_builder_function_call 
It can be useful not just to create functions, but also being able to
call them. This adds the spirv_builder-helper for this.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
(cherry picked from commit 47d67912bd)
 2022-09-14 14:37:00 -07:00
Erik Faye-Lund
1ddca52324 zink: type_main -> type_void_func 
This type will be reused later on, so let's have the name describe what
is *is*, not what it's *used for*.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
(cherry picked from commit 41dfed6e12)
 2022-09-14 14:37:00 -07:00
Jordan Justen
b406a3c6ee intel/pci_ids: Add 0x468b ADL-S PCI-id 
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
(cherry picked from commit f4c44444ad)
 2022-09-14 14:36:58 -07:00
Jordan Justen
f08ddee3a5 intel/pci_ids: Update ADL-S strings 
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
(cherry picked from commit 6ca37aabfb)
 2022-09-14 14:36:57 -07:00
Gert Wollny
fc014e713a r600/sfn: Use a low number for unused target register 
This reduces the number of registers reserved by the shader
units and makes more threads possible.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6856

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit bf4234d088)
 2022-09-14 14:36:57 -07:00
Gert Wollny
ad7ec70ca6 r600: Fix reporting TGSI IR support 
When NIR is not explicitely enabled we still support TGSI.

Fixes: 33765aa92a
    r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 90f99369ae)
 2022-09-14 14:36:56 -07:00
Gert Wollny
29415adbaa r600/sfn: Use a heuristic to keep SSBO setup and store close 
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

v2: do handling in shader block to be thread save (hinted to by Filip)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit c81fe5b235)
 2022-09-14 14:36:56 -07:00
Gert Wollny
b84c8968c7 r600/sfn: Don't scan the whole block for ready instructions 
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.

This reduces the time needed to run the scheduler significantly.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 1f5dccb760)
 2022-09-14 14:36:55 -07:00
Gert Wollny
e201b751fc r600/sfn: Don't schedule GDS instructions early 
Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b48
    r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 79eabb8130)
 2022-09-14 14:36:55 -07:00
Gert Wollny
36a66a3124 r600/sfn: Don't tag mem-ring and stream instructions as exports 
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.

When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.

This fixes
  spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit fd71cd0b6a)
 2022-09-14 14:36:54 -07:00
Gert Wollny
7bcd2e6767 r600/sfn: Handle color0 writes all on R700 like on EG 
Fixes: 069f3869ac
    r600/sfn: Fix color outputs when color0 writes all

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 3a0f085837)
 2022-09-14 14:36:53 -07:00
Lucas Stach
ab35b97b78 etnaviv: add debug option to disable linear PE feature 
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 43eb5e777e)
 2022-09-14 14:36:52 -07:00
Lucas Stach
1a79d5e861 etnaviv: use linear PE rendering only on properly aligned surfaces 
When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.

The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.

For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.

CC: mesa-stable #22.2
Fixes: 53445284a4 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit ea8fc9592c)

Conflicts:
	src/gallium/drivers/etnaviv/etnaviv_surface.c
 2022-09-14 14:36:51 -07:00
Lucas Stach
0e5bf558ef etnaviv: move checking for MC2.0 for TS into screen init 
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.

Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 09953d7b75)
 2022-09-14 13:58:58 -07:00
Kenneth Graunke
f5ae4c35fe iris: Use linear for exported resources if we can't convey tiling 
If we have modifiers, we can use those to convey the tiling of exported
resources.  If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.

If we have neither, then we have to fall back to linear.

Fixes: e658835436 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
(cherry picked from commit 71ace23fa7)
 2022-09-14 13:58:58 -07:00
Yiwei Zhang
c8ba293450 venus: avoid feedback for external fence 
Sync fd fence export implies a payload reset operation, and application
can immediately do another submission with the same fence after export.
Concurrent use of the same feedback slot is incorrect. Keeping a list of
feedback slots for sync_fd external fence is a bit over designed given
those fences are usually not checked or waited by the app, but will hand
off the ownership via sync fd to an external client.

Fixes: d7f2e6c8d0 ("venus: add fence feedback")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
(cherry picked from commit 5457f4c0a4)
 2022-09-14 13:58:58 -07:00
Yiwei Zhang
27fb80d64d venus: fix external memory ext filtering 
Fixes: 390722620e ("venus: clean up vn_device_fix_create_info")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
(cherry picked from commit 9c5a7ffbd8)
 2022-09-14 13:58:58 -07:00
Qiang Yu
2e3afb6765 winsys/amdgpu: fix non-page-aligned sparse buffer creation 
ARB_sparse_buffer does not require sparse buffer size to be
page aligned. So we need to align it before VM ops as KMD
will check whether it's aligned and return EINVAL if not.

Fixes: 667da4eaed ("winsys/amdgpu: sparse buffer creation / destruction / commitment")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
(cherry picked from commit 4fc9125ca2)
 2022-09-14 13:58:58 -07:00