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34 Commits

Author SHA1 Message Date
Alyssa Rosenzweig
6a183a9ffd agx: Add iterators for phi/non-phi instructions 
We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
c17fcbaa2f agx: Account for mask when writing registers 
To use fewer registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
 2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
4f85a7be8c agx: Make p_combine take a dynamic src count 
For larger vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
 2022-09-13 16:04:28 +00:00
Alyssa Rosenzweig
10c9aceadf agx: Plumb through nir_op_txf 
nir_op_txf maps to AGX's texture_load, which is encoded like
texture_sample. The one outstanding question with this commit is the
rules for the sample required ... in NIR and APIs (including Metal), txf
is samplerless, but the AGX instruction consumes a sampler. Hopefully
any sampler will do, though?

Passes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
 2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig
17168162fb agx: Remove p_extract 
It's now unused. We didn't have coalescing for it anyway, splits are the
preferred alternative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
 2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig
c1900cb951 agx: Handle type-changing splits 
If we want to break down a 64-bit value into its 32-bit halves, we want
to be able to use a split for this:

   lo, hi = split long

Extend the RA to handle this case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
 2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig
8c2e626064 agx: Align 64-bit register pairs 
This seems to be necessary for correct operation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
 2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig
744b4a0f7f agx: Rename varying load instructions 
Unlike Mali (where I borrowed the old names from), these are not loads
in the memory sense. They are simply register loads and arithmetic.
Rename accordingly, using PowerVR names and public Apple names as a
guide.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
 2022-08-07 20:43:53 -04:00
Alyssa Rosenzweig
18ef9398de agx: Remove nir_register support 
We don't use it anymore, now that we can handle SSA form. Gets rid of
the most gross hack in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
1c6bd0357f agx: Update RA comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
4498799822 agx: Remove identity moves 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
860832e41b agx: Split up RA from post-RA lowering 
This allows us to validate results in the middle.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
ea065537cb agx: Lower phi nodes to parallel copies 
Now we have an SSA RA :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
a2a947031a agx: Mark the logical ends of blocks 
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
3f1e926bf4 agx: Use a dynarray for predecessors 
This imposes a fixed ordering, allowing phi sources to be implicitly ordered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
d06394095b agx: Optimize p_split(kill) specially 
Let's make sure these are allocated optimally.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
e16ad8f443 agx: Lower p_split after RA 
Using existing regalloc infrastructure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
4fc023ed42 agx: Use a transfer graph for parallel copies 
Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.

Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.

Original implementation by Connor Abbott.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig
ff660dd637 agx: Track write registers more accurately 
We may not write a full 32-bit vec4, don't be so pessimistic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig
0c82b5c99c agx: Note that RA proceeds in dominance-order 
This is an important invariant for SSA-based RA to work.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig
81477f3809 agx: Implement some shader-db stats 
Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 21:58:29 -04:00
Alyssa Rosenzweig
96c98e0d25 agx: Define p_extract for type converts 
Useful for grabbing the high 32-bit word of a 64-bit value.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
 2021-07-24 17:25:40 -04:00
Alyssa Rosenzweig
3c1f754a71 agx: Handle load_instance_id 
Preloaded into r6, as predicted.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
 2021-07-24 15:12:18 -04:00
Alyssa Rosenzweig
465224379c agx: Plug memory leak in register allocator 
Fixes: 85e18deb18 ("agx: Assign registers locally")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reported-by: Coverity
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
 2021-07-24 15:00:22 -04:00
Alyssa Rosenzweig
7848100f27 agx: Use consistent ncomps 
Fixes register allocation failure in:
dEQP-GLES3.functional.ubo.single_basic_array.shared.row_major_mat4_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
 2021-07-24 14:55:16 -04:00
Alyssa Rosenzweig
cce1a2fc19 agx: Dump register file when failing to allocate 
Usually shows a bug.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
 2021-07-24 14:54:34 -04:00
Alyssa Rosenzweig
1d0008734c agx: Ensure we don't overallocate registers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
 2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig
85e18deb18 agx: Assign registers locally 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
 2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig
15b49a6795 agx: Count read registers as well 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
 2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig
2e1ba82060 agx: Count write registers, not components 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
 2021-07-05 20:56:04 +00:00
Alyssa Rosenzweig
ebd25e7ee7 agx: Pull out agx_write_components 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
 2021-07-05 20:56:04 +00:00
Alyssa Rosenzweig
3d3e4928b2 agx: Add ld_vary_flat opcode 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
 2021-07-05 20:56:03 +00:00
Alyssa Rosenzweig
1164c992cf agx: Add ld_tile opcode 
Variant of st_tile.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10720>
 2021-05-09 23:29:45 -04:00
Alyssa Rosenzweig
c215895eae agx: Add a trivial register allocator 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
 2021-05-02 17:41:12 -04:00