Commit Graph

77295 Commits

Author SHA1 Message Date
Marek Olšák
c886422656 tgsi/ureg: remove index parameter from ureg_DECL_system_value
It can be trivially derived from the number of already declared system
values. This allows ureg users not to worry about which index to choose.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-08 20:06:22 +01:00
Marek Olšák
91e8f2b0a5 st/mesa: remove dead code from mesa_to_tgsi
These aren't part of ARB_fragment_program.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-08 20:06:22 +01:00
Edward O'Callaghan
cb513485a0 radeon, si: Use TGSI chan name defines in lp_build_emit_fetch() calls
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-08 12:18:36 -05:00
Edward O'Callaghan
b42254eff3 gallium/aux: Use TGSI chan name defines inplace of literals
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-08 12:18:24 -05:00
Nicolai Hähnle
d6db7ceedf mesa: check that internalformat of CopyTexImage*D is not 1, 2, 3, 4
The piglit copyteximage check has recently been augmented to test this, but
apparently it hasn't been fixed in Mesa so far.

This language also already appears in the OpenGL 2.1 spec (Ian).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-08 10:58:27 -05:00
Jason Ekstrand
72bff62e7f nir/spirv: Add support for SSBO atomics 2016-01-07 22:13:46 -08:00
Jason Ekstrand
fe57ad62a6 nir/spirv: Rework UBOs and SSBOs
This completely reworks all block load/store operations.  In particular, it
should get row-major matrices working.
2016-01-07 22:13:46 -08:00
Chad Versace
1818463733 anv/gen9: Fix cube surface state
For gen9 SURFTYPE_CUBE, the RENDER_SURFACE_STATE's Depth,
MinimumArrayElement, and RenderTargetViewExtent is in units of full
cubes and so must be divided by 6.

Fixes 'dEQP-VK.pipeline.image.view_type.cube_array.cube_array.*'.

Now all of 'dEQP-VK.pipeline.image.*' passes.
2016-01-07 17:20:25 -08:00
Chad Versace
24d82a3f79 anv/gen8: Refactor genX_image_view_init()
Drop the temporary variables for RENDER_SURFACE_STATE's Depth and
RenderTargetViewExtent. Instead, assign them in-place.

This simplifies the next commit, which fixes gen9 cube surfaces.
2016-01-07 17:20:25 -08:00
Kristian Høgsberg Kristensen
1b1dca75a4 vk: Make sure we emit binding table pointers after push constants
SKL needs this to make sure we flush the push constants. It gets a
little tricky, since we also need to emit binding tables before push
constants, since that may affect the push constants (dynamic buffer
offsets and storage image parameters).  This patch splits emitting
binding tables from emitting the pointers so that we can emit push
constants after binding tables but before emitting binding table
pointers.
2016-01-07 16:31:57 -08:00
Kristian Høgsberg Kristensen
a18b5e642c vk: Implement VK_QUERY_RESULT_WITH_AVAILABILITY_BIT 2016-01-07 16:31:57 -08:00
Kristian Høgsberg Kristensen
bbf3fc815b vk: Add missing DepthStallEnable to OQ pipe control 2016-01-07 16:31:57 -08:00
Kristian Høgsberg Kristensen
067dbd7a17 vk: Issue PIPELINE_SELECT before setting up render pass
We need to make sure we're selected the 3D pipeline before we start
setting up depth and stencil buffers.
2016-01-07 16:31:57 -08:00
Jordan Justen
d24e88b98e anv/gen7: Setup state to enable barrier() function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-07 17:11:46 -08:00
Jordan Justen
36a2304686 anv/gen8: Setup state to enable barrier() function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-07 17:11:46 -08:00
Jason Ekstrand
040e314143 i965/compiler: Enable more lowering in NIR
We don't need these for GLSL or ARB, but we need them for SPIR-V

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-07 16:14:42 -08:00
Jason Ekstrand
d00abcc283 nir/algebraic: Add more lowering
This commit adds lowering options for the following opcodes:

 - nir_op_fmod
 - nir_op_bitfield_insert
 - nir_op_uadd_carry
 - nir_op_usub_borrow

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-07 16:14:38 -08:00
Jason Ekstrand
b0d4ee520e nir/opcodes: Fix up uadd_carry and usub_borrow
Both were defined as returning bool but the gpu_shader5 functions are
defined to return int.  Also, we had the parameters for usub borrwo
backwards in the folding expression.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-07 16:14:25 -08:00
Ilia Mirkin
67b31b3c59 nvc0: add ARB_indirect_parameters support
I chose to make separate macros for this due to the additional
complexity and extra scratch usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
9a54ccf30a st/mesa: expose ARB_indirect_parameters when the backend driver allows
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
e1eab5a76f mesa: add support for ARB_indirect_parameters draw functions
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
9327e2d312 mesa: add parameter buffer, used for ARB_indirect_parameters
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
b3e2c21fe5 glapi: add ARB_indirect_parameters definitions
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
7ca67c752b nvc0: add support for real ARB_multi_draw_indirect
The draw groups are now split up into groups of 32 if there's a
non-packed stride, or in groups of 400-500 if the draw data is packed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
d3e43baffe nvc0: adjust indirect draw macros to handle multiple draws at once
These are still invoked one at a time, but the underlying macro can
handle multiple draws.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
2860f20859 st/mesa: add support for new mesa indirect draw interface
This shifts all indirect draws to go through the new function. If the
driver doesn't have support for multi draws, we break those up and
perform N draws. Otherwise, we pass everything through for just a single
draw call.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
d67b9ba9a1 gallium: add caps to expose support for multi indirect draws
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
3e11656694 gallium: add sufficient draw interface to allow new indirect features
This makes it possible to support indirect multidraws as well as having
the number of such draws to come from a separate GPU resource.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-07 18:38:46 -05:00
Ilia Mirkin
60d0cfd429 vbo: create a new draw function interface for indirect draws
All indirect draws are passed to the new draw function. By default
there's a fallback implementation which pipes it right back to
draw_prims, but eventually both the fallback and draw_prim's support for
indirect drawing should be removed.

This should allow a backend to properly support ARB_multi_draw_indirect
and ARB_indirect_parameters.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-07 18:38:45 -05:00
Roland Scheidegger
2923c7a0ed llvmpipe: do 64bit plane calculations in the sse path
The sse path was pretty much disabled for practical purposes because the
largest allowed fb size was 128x128. So, adapt it for 64bit plane calculations.
This is actually not that difficult, though a problem is that we can't do
a signed 32x32->64bit mul, only unsigned, so need to fix that up. Overall,
the code still looks reasonable, though it's not like changes there in
setup really make much of a difference in the end...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-01-08 00:34:14 +01:00
Roland Scheidegger
fad283ba9e llvmpipe: don't store eo as 64bit int
eo, just like dcdx and dcdy, cannot overflow 32bit.
Store it as unsigned though just in case (it cannot be negative, but
in theory twice as big as dcdx or dcdy so this gives it one more bit).
This doesn't really change anything, albeit it might help minimally on
32bit archs.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-01-08 00:34:14 +01:00
Roland Scheidegger
b61b9a377e llvmpipe: use aligned data for the assembly program in setup
Back in the day (before 24678700ed) the values
were not actually in a struct but even then I can't see why we didn't simply
align the values. Especially since it's trivial to do so.
(Not that it actually matters since the code is pretty much unused for now.)

Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
2016-01-08 00:34:13 +01:00
Roland Scheidegger
9db7309595 draw: initialize prim header flags when clipping lines
Otherwise, clipped lines would have undefined stippling reset bit if line
stippling is enabled.
(Untested, and I just assume copying over the bits from the original line
is actually the right thing to do.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-08 00:34:13 +01:00
Roland Scheidegger
64da11f052 draw: fix line stippling with unfilled prims
The unfilled stage was not filling in the prim header, and the line stage
then decided to reset the stipple counter or not based on the uninitialized
data. This causes some failures in conform linestipple test (albeit quite
randomly happening depending on environment).
So fill in the prim header in the unfilled stage - I am not entirely sure
if anybody really needs determinant after that stage, but there's at least
later stages (wide line for instance) which copy over the determinant as well.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-01-08 00:34:13 +01:00
Timothy Arceri
5cf156c6b4 glsl: replace null check with assert
This was added in 54f583a20 since then error handling has improved.

The test this was added to fix now fails earlier since 01822706ec

Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-08 09:12:45 +11:00
Nicolai Hähnle
051603efd5 i965: use _mesa_delete_buffer_object
This is more future-proof, plugs the memory leak of Label and properly
destroys the buffer mutex.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-07 17:07:12 -05:00
Nicolai Hähnle
1b74c02e83 i915: use _mesa_delete_buffer_object
This is more future-proof, plugs the memory leak of Label and properly
destroys the buffer mutex.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-07 17:07:09 -05:00
Nicolai Hähnle
8882b46226 radeon: use _mesa_delete_buffer_object
This is more future-proof, plugs the memory leak of Label and properly
destroys the buffer mutex.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-07 17:07:03 -05:00
Nicolai Hähnle
1c2187b1c2 st/mesa: use _mesa_delete_buffer_object
This is more future-proof than the current code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2016-01-07 17:06:58 -05:00
Nicolai Hähnle
6aed083b93 mesa/bufferobj: make _mesa_delete_buffer_object externally accessible
gl_buffer_object has grown more complicated and requires cleanup. Using this
function from drivers will be more future-proof.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-07 17:05:54 -05:00
Chad Versace
4c7f4c25d0 anv/meta: Fix hardcoded format size in anv_CmdCopy*
When looping through VkBufferImageCopy regions, for each region we
incremented the offset into the VkBuffer assuming the format size was 4.

Fixes CTS tests dEQP-VK.pipeline.image.view_type.cube_array.3d.* on
Skylake.
2016-01-07 13:56:58 -08:00
Oded Gabbay
f41b6cfb07 llvmpipe: use sse2 conv code for altivec
In lp_build_conv() and lp_build_conv_auto(), there is a special case of
conversion when sse2 is present. That code path is suitable without any
changes to altivec, because all the functions that are called in that
code path already support altivec.

This patch increase the FPS in POWER arch across the board
between 10%-25%

I checked ipers, glxgears, glxspheres64, openarena, xonotic and glmark2.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-07 22:07:02 +02:00
Chad Versace
a50c78a5cf isl: Add missing break statement in array pitch calculation
Fixes regression in ed98c374bd3f1952fbab3031afaf5ff4d178ef41.
2016-01-07 11:08:12 -08:00
Chad Versace
d1e6c1b29b isl/gen9: Fix array pitch of 3d surfaces
For tiled 3D surfaces, the array pitch must aligned to the tile height.

From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:

   Tile Mode != Linear: This field must be set to an integer multiple of
   the tile height

Fixes CTS tests 'dEQP-VK.pipeline.image.view_type.3d.format.r8g8b8a8_unorm.*'.
Fixes Crucible tests 'func.miptree.r8g8b8a8-unorm.aspect-color.view-3d.*'.
2016-01-07 11:04:17 -08:00
Chad Versace
0af77fe5b6 isl: Refactor func isl_calc_array_pitch_sa_rows
Update the function to calculate the array pitch is *element rows*, and
it rename it accordingly to isl_calc_array_pitch_el_rows.
2016-01-07 11:04:17 -08:00
Jordan Justen
2f0a10149c isl: Assert that alignments are not 0 for isl_align
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-07 10:37:35 -08:00
Jordan Justen
4d68c477ad anv: Assert that alignments are not 0 for align_*
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-07 10:37:35 -08:00
Jordan Justen
be91f23e3b isl: Fix image alignment calculation
The previous code was resulting in an alignment of 0.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-07 10:37:35 -08:00
Marek Olšák
bca18057a3 radeonsi: adjust the parameters of si_shader_dump
The function will be extended to dump all binaries shaders will consist of,
so si_shader* makes sense here.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
Marek Olšák
0a51b010e5 radeonsi: move si_shader_dump call out of si_compile_llvm
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00