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Author SHA1 Message Date
Mary Guillemard
3b69edf825 pan/genxml: Enforce explicit packed types on pan_[un]pack 
Provide a pan_cast_and_[un]pack() to help with the transition.
Those helpers should only be used when the caller is sure the
destination is big enough to emit the descriptor.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Mary Guillemard
bd80037441 pan/genxml: Move [un]pack internals to use packed structs 
We are now strongly typing everything, pan_[un]pack wil enforce this at
the API level next.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Boris Brezillon
b9caca64f2 pan/genxml: Generate MALI_XXX_PACKED_T macros 
Will be useful to easily define packed type variables from the
pan_[un]pack() functions, which we'll need during the pan_pack
revamp.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Mary Guillemard
39d8b56c4a pan/genxml: Emit struct details before pack function 
We are going to use packed structs in [un]pack next so we need those to
be emitted before them.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Mary Guillemard
95435a788d pan/genxml: Switch unpack to use uint32_t 
Makes this match pack.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Boris Brezillon
ab1cd917ad pan/genxml: Include pan_pack_helpers.h instead of copying it 
The generic bits in autogen pack helpers files were extracted in a
common header, so let's include it from the autogenerated file rather
than copying its content there.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Boris Brezillon
39461e5818 pan/genxml: s/PAN_PAN_HELPERS_H/PAN_PACK_HELPERS_H/ 
Fix a typo in the multi-inclusion guard.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32962>
 2025-01-10 18:27:27 +00:00
Eric Engestrom
519f4bba6b docs/release-calendar: push the 25.0 branchpoint back by 2 weeks 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32975>
 2025-01-10 18:19:06 +00:00
Michael Cheng
c3c05ffb5f intel : Expose Shader hashes for utrace and Perfetto 
This patch exposes shader hashes (computes and draws) to Perfetto and
utrace. By including these hashes in traces, developers can correlate
compute and draw calls with their assoicated ASM dumps when analyzing
the traces.

To achieve this, intel_tracepoint.py has been reworked to preprocess
tracepoint arguments dynamically. Any argument containing "hash" in its
variable name is now forrmated as hexadecimal before being passed to the
tracepoint definition.

Signed-off-by: Michael <michael.cheng@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32708>
 2025-01-10 17:38:16 +00:00
Boris Brezillon
6f8fb6d73d panfrost/ci: Add panvk and panfrost to the debian-x86_32 job 
Useful to catch compile-time regressions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32938>
 2025-01-10 15:53:36 +00:00
Boris Brezillon
dc1b988273 panvk: Fix panvk_priv_mem_bo() on 32-bit platforms 
Masking with an ~7ull promotes the value to 64-bit, leading
to a size mismatch when we cast it to a pointer.

Make sure we're using an uintptr_t type for the mask.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32938>
 2025-01-10 15:53:36 +00:00
Boris Brezillon
134f965b88 panvk: Fix an alignment issue on x86 
On x86-32, long long are aligned on 4-bytes only, which breaks
the assumption we had about our sysvals struct layouts.

Define an aligned_u64 embedding the alignment attribute to
keep the alignment sane.

While at it, enforce this alignment with an alignment attribute
on the struct itself.

This fixes the build on x86-32, and should do what we expect,
though it's not been tested in practice.

Fixes: ae76a6a045 ("panvk: Pack push constants")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12429
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32938>
 2025-01-10 15:53:36 +00:00
Rhys Perry
2b10930b48 aco: use VOP3 v_mov_b16 if necessary 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Backport-to: 24.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32944>
 2025-01-10 15:05:00 +00:00
Rhys Perry
46787fc2d0 aco/util: fix bit_reference::operator&= 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Backport-to: 24.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32944>
 2025-01-10 15:05:00 +00:00
Erik Faye-Lund
4ff5672730 docs: update panvk status 
We enabled fragmentStoresAndAtomics, but forgot to update this file.
Also add drawIndirectFirstInstance, which I missed last time I updated
the new features.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32960>
 2025-01-10 11:35:56 +00:00
Lucas Stach
3a0d4c4203 ci/etnaviv: drop failures caused by missing vertex attributes 
Now that we fill in a dummy state, instead of allowing the FE to
run with undefined state when no vertex attributes are present
we can drop the failures that were caused by this issue.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32947>
 2025-01-10 10:57:58 +00:00
Lucas Stach
5ca8feb28b etnaviv: fix rendering without vertex buffers/attributes 
The hardware doesn't allow to disable all vertex attribute streams,
so we end up with random FE state when a draw without vertex
attributes is encountered. Plug in a dummy attribute and vertex
buffer to avoid this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32947>
 2025-01-10 10:57:58 +00:00
Lucas Stach
bca5ef70a4 etnaviv: split dummy RT backing store from reloc 
The dummy BO used as backing store for the dummy render target
can be reused for other usages where we don't care about the
actual content of the buffer. Split it out from the dummy RT
reloc to make this more clear.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32947>
 2025-01-10 10:57:58 +00:00
David Rosca
c23df7e790 frontends/va: Only report surface alignment when non-zero 
Otherwise this means the alignment is 1x1 which is wrong.

Fixes: b24748a93a ("frontends/va: add surface alignment attribute")
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32923>
 2025-01-10 10:10:41 +00:00
Lukas Lipp
c0ef005bf4 wsi: Fix wrong function name for lvp wsi metal surface 
Fixes: a42c2293ab
Reviewed-by: Aleksi Sapon <aleksi.sapon@autodesk.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32878>
 2025-01-10 09:27:02 +00:00
David Rosca
42595eb52e radeonsi/vcn: Fix crash when failing to allocate internal buffers 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11725
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32901>
 2025-01-10 07:43:08 +00:00
Caio Oliveira
c9e667b7ad intel/elk: Remove uses of VLAs 
Was causing trouble in some build configurations, we don't really need
them.  Unless there's a good reason, defaults to use ralloc for
consistency with the larger codebase.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Caio Oliveira
172c1ab984 intel/elk: Add ELK_MAX_MRF_ALL for static allocating arrays 
Replace usage of variable length arrays.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Caio Oliveira
4d43ee0dd6 intel/brw: Remove uses of VLAs 
Was causing trouble in some build configurations, we don't really need
them.  Use ralloc for consistency.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Caio Oliveira
faf4c35b74 intel/compiler: Use linear allocator for ACP trees in copy-prop 
Replace usage of variable length array.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Caio Oliveira
d35b6919a5 util: Add operator new[] to linear context helper declarations 
This allow us to allocate arrays with `new (lin_ctx) MyStruct[10]`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Caio Oliveira
e6a3770433 intel/compiler: Use INFINITY spill cost to represent no_spill 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
 2025-01-10 07:05:35 +00:00
Marek Olšák
8ba718fb7d radeonsi/gfx12: use ACO for streamout because it's faster 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 23:37:55 -05:00
Marek Olšák
239840556f radeonsi/gfx12: use ACO if LLVM is 19 or older 
LLVM 19 is missing a SALU hazard fix.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 23:37:55 -05:00
Marek Olšák
b05fa7d575 radeonsi/gfx12: set DIS_PG_SIZE_ADJUST_FOR_STRIP after shader compilation 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 23:37:55 -05:00
Marek Olšák
4cfa4e9dd7 radeonsi/gfx12: enable alt_hiz_logic 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 23:37:55 -05:00
Marek Olšák
1b405a12e0 radeonsi: only set BREAK_PRIMGRP/WAVE_AT_EOI when TES/GS need PrimID sysval after TES 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 23:37:52 -05:00
Marek Olšák
f06a103eea radeonsi: don't set BREAK_PRIMGRP/WAVE_AT_EOI when tessellation is disabled 
It's not required and it decreases performance.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32957>
 2025-01-09 22:44:44 -05:00
Konstantin Seurer
963f8fff1e meson: Include the loader subdir when building lavapipe 
This could be skipped when building only lavapipe with only x11.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32883>
 2025-01-10 01:24:11 +00:00
Konstantin Seurer
23a96b1537 lavapipe: Check the pool type in handle_reset_query_pool 
Avoids a segmentation fault when resetting acceleration structure
queries.

Fixes: 897ccbd ("lavapipe: Implement VK_KHR_acceleration_structure")
Closes: #12289
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32616>
 2025-01-10 00:58:17 +00:00
Konstantin Seurer
fac818bdb3 meson: Require glslangValidator when building lavapipe 
The tool is required by the runtime for acceleration structures.
Lavapipe uses some of those runtime helpers and will use more of them in
the future (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31426),
especially those that have a hard requirement for the tool.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12412
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12437
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32882>
 2025-01-10 00:08:30 +00:00
José Roberto de Souza
022671f2c4 iris: Rename BO_ALLOC_COHERENT to BO_ALLOC_CACHED_COHERENT 
BO_ALLOC_COHERENT is not a good name as it can mean 2 different memory
types: cached+coherent and uncached+coherent, so
here renaming it to BO_ALLOC_CACHED_COHERENT that is more close to the
usage that we have for it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28774>
 2025-01-09 23:40:53 +00:00
José Roberto de Souza
3db38d05d4 iris: Drop BO_ALLOC_COHERENT from iris_utrace_create_ts_buffer() 
timestamp is not modified by CPU, it is written by GPU and just read
by CPU.
As all BOs in Iris are CPU coherent, there is no need to keep this
flag.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28774>
 2025-01-09 23:40:52 +00:00
Timur Kristóf
dd980d2b28 radv: Only print "testing use only" message on GFX12+. 
This message has been confusing users, especially now that
popular toolkits such as Gtk started using a Vulkan renderer.

Printing a message on non-conformant implementations is also
actually not required. So let's remove it.

We haven't fully finished the GFX12 implementation yet,	but on
all other hardware, RADV should	work just fine,	and is definitely
not meant for "testing use only".

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12314
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32930>
 2025-01-09 23:16:48 +00:00
Mike Blumenkrantz
fafa71b6ad zink: use internal map flag for qbos 
DONTBLOCK is sort of almost good enough except that the api frontend
can also use this and it can't use the full power of Trust Me Buddy™
that qbo maps require

this causes unnecessary ioctl syncs, which annihilates perf in games
that constantly check query results

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31823>
 2025-01-09 22:45:27 +00:00
Mike Blumenkrantz
17ca1bfbf7 zink: rework query result checking 
this allows a return without checking syncobj, avoiding overhead,
but when a query still isn't completing after multiple checks then
try checking the pool directly

this circumvents the usual qbo mechanism in specific cases (e.g., Everspace)
where an app fires off a million timestamp queries and the overhead of
checking a timeline semaphore kills perf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31823>
 2025-01-09 22:45:27 +00:00
Marek Olšák
e640d5a9c3 amd: vectorize SMEM loads aggressively, allow overfetching for ACO 
If there is a 4-byte hole between 2 loads, they are vectorized. Example:
    load 4 + hole 4 + load 8 -> load 16
This helps GLSL uniform loads, which are often sparse. See the code for more
info.

RADV could get better code by vectorizing later.

radeonsi+ACO - TOTALS FROM AFFECTED SHADERS (45482/58355)
  Spilled SGPRs: 841 -> 747 (-11.18 %)
  Code Size: 67552396 -> 65291092 (-3.35 %) bytes
  Max Waves: 714439 -> 714520 (0.01 %)

This should have no effect on LLVM because ac_build_buffer_load scalarizes
SMEM, but it's improved for some reason:

radeonsi+LLVM - TOTALS FROM AFFECTED SHADERS (4673/58355)
  Spilled SGPRs: 1450 -> 1282 (-11.59 %)
  Spilled VGPRs: 106 -> 107 (0.94 %)
  Scratch size: 101 -> 102 (0.99 %) dwords per thread
  Code Size: 14994624 -> 14956316 (-0.26 %) bytes
  Max Waves: 66679 -> 66735 (0.08 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29399>
 2025-01-09 22:01:54 +00:00
Marek Olšák
e0c343888f radeonsi: lower descriptors sooner to allow vectorizing descriptor loads 
The comment was wrong.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29399>
 2025-01-09 22:01:54 +00:00
Marek Olšák
abd5216ae8 ac,radeonsi: scalarize overfetching loads 
There is nothing preventing ACO from generating loads with unused
components. This happens often with GLSL uniforms. Some of those loads
are partially re-vectorized after this.

radeonsi+ACO:

TOTALS FROM AFFECTED SHADERS (19564/58918)
  VGPRs: 732900 -> 728448 (-0.61 %)
  Spilled SGPRs: 429 -> 433 (0.93 %)
  Code Size: 38446004 -> 38485612 (0.10 %) bytes
  Max Waves: 305440 -> 305549 (0.04 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29399>
 2025-01-09 22:01:54 +00:00
Sagar Ghuge
710624fcc0 anv: Use 3DSTATE_URB_ALLOC_* instructions 
Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
 2025-01-09 21:26:40 +00:00
Sagar Ghuge
604a384e97 blorp: Use 3DSTATE_URB_ALLOC_* instructions 
Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
 2025-01-09 21:26:40 +00:00
Sagar Ghuge
190bde3969 iris: Use 3DSTATE_URB_ALLOC_* instructions 
Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
 2025-01-09 21:26:40 +00:00
Sagar Ghuge
0bca8da981 intel/genxml: Update URB related instructions and structures 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
 2025-01-09 21:26:40 +00:00
Marek Olšák
58a88bbdb9 ac/nir/ngg: export positions after streamout to improve performance 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32686>
 2025-01-09 20:47:16 +00:00
Marek Olšák
fc73749d6c ac/nir/ngg: fold so_vertex_index * so_stride into immediate offset 
Instead of using a different voffset VGPR per streamout vertex,
point voffset to the first vertex for all 3 vertices because
the stride and vertex index are constant and can be in the immediate
offset.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32686>
 2025-01-09 20:47:16 +00:00