With the automatic-TCS creation, we won't have a prog, but still need to
upload push constants.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tessellation control shaders are optional, but evaluation shaders will
always be present when using tessellation. However, we'll always enable
the TCS (HS) hardware stage when using tessellation - we'll just create
a program on the fly.
That program, however, won't have a gl_program or gl_shader_program.
So we shouldn't check brw->tess_ctrl_program or
shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] - if we want to know
whether tessellation is enabled, we should look for a TES.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This is trying to enforce the fact that the hardware requires HS, TE,
and DS to be enabled or disabled together. But it's kind of an ad-hoc
attempt, and not too useful.
More importantly, we aren't going to have a gl_shader_program for the
TCS which is automatically generated when none is present. (We'll just
handle it in the driver backend.) So, these will trip for no reason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
For several reasons, I don't think it's particularly useful to have
separate flags:
1. Most of the time, tessellation shaders are paired, so both will be
replaced at the same time.
2. The data layout is tightly coupled. Both need to agree on the number
of per-patch slots in the VUE map. Even adding extra TCS outputs
that aren't read by the TES will trigger the need for recompiles.
3. The TCS is optional from an API perspective, but required by the
hardware whenever tessellation is enabled. So, atoms that deal with
the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
rather than brw->tess_ctrl_program to tell whether tessellation is
enabled.
So, not only is it unlikely to be useful, it's a bit confusing to get
right. Simply using one flag for both simplifies this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
If there's no evaluation shader, tessellation is disabled. The upload
functions would just bail. Instead, don't bother calling them.
This will simplify the optional-TCS case a bit, as brw_upload_tcs can
assume that we're doing tessellation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
I need access to glsl_type::vec2_type from C. Wrapping vec() also gives
us access to vec3 if we need it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Instead of performing the read-modify-write cycle in glsl->nir, we can
simply emit a partial writemask. For locals, nir_lower_vars_to_ssa will
do the equivalent read-modify-write cycle for us, so we continue to get
the same SSA values we had before.
Because glsl_to_nir calls nir_lower_outputs_to_temporaries, all outputs
are shadowed with temporary values, and written out as whole vectors at
the end of the shader. So, most consumers will still not see partial
writemasks.
However, nir_lower_outputs_to_temporaries bails for tessellation control
shader outputs. So those remain actual variables, and stores to those
variables now get a writemask. nir_lower_io passes that through. This
means that TCS outputs should actually work now.
This is a functional change for tessellation control shaders.
v2: Relax the nir_validate assert to allow partial writemasks.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Tessellation control shaders need to be careful when writing outputs.
Because multiple threads can concurrently write the same output
variables, we need to only write the exact components we were told.
Traditionally, for sub-vector writes, we've read the whole vector,
updated the temporary, and written the whole vector back. This breaks
down with concurrent access.
This patch prepares the way for a solution by adding a writemask field
to store_var intrinsics, as well as the other store intrinsics. It then
updates all produces to emit a writemask of "all channels enabled". It
updates nir_lower_io to copy the writemask to output store intrinsics.
Finally, it updates nir_lower_vars_to_ssa to handle partial writemasks
by doing a read-modify-write cycle (which is safe, because local
variables are specific to a single thread).
This should have no functional change, since no one actually emits
partial writemasks yet.
v2: Make nir_validate momentarily assert that writemasks cover the
complete value - we shouldn't have partial writemasks yet
(requested by Jason Ekstrand).
v3: Fix accidental SSBO change that arose from merge conflicts.
v4: Don't try to handle writemasks in ir3_compiler_nir - my code
for indirects was likely wrong, and TTN doesn't generate partial
writemasks today anyway. Change them to asserts as requested by
Rob Clark.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3]
Patch makes following changes for interface matching:
- do not try to match builtin variables
- handle swizzle in input name, as example 'a.z' should
match with 'a'
- add matching by location
- check that amount of inputs and outputs matches
These changes make interface matching tests to work in:
ES31-CTS.sepshaderobjs.StateInteraction
The test still does not pass completely due to errors in rendering
output. IMO this is unrelated to interface matching.
Note that type matching is not done due to varying packing which
changes type of variable, this can be added later on. Preferably
when we have quicker way to iterate resources and have a complete
list of all existed varyings (before packing) available.
v2: add spec reference, return true on desktop since we do not
have failing cases for it, inputs and outputs amount do not
need to match on desktop.
v3: add some more spec reference, remove desktop specifics since
not used for now on desktop, add match by location qualifier,
rename input_stage and output_stage as producer and consumer
as suggested by Timothy.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
The i965 driver uses this function to decide if it can disable the
FS unit in the absence of color/depth writes. We don't want to disable
the unit in the presence of SSBOs, since the fragment shader could
be writing to it.
We could go a step further and check not just for the presence of SSBOs
but also if the shader code writes to them. Does not look worth the trouble
though and we are not doing this for atomic buffers either anyway.
v2: put this into a generic _mesa_active_fragment_shader_has_side_effects
function instead of having one specific for SSBOs (Jason).
Fixes the following CTS test:
ES31-CTS.shader_storage_buffer_object.advanced-usage-sync-vsfs
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
On Haswell we need to set the UAV_ONLY WM state bit when there are no colour
or depth buffer writes and on all hardware we should set the early
depth/stencil control field to PSEXEC unless early fragment tests are enabled
to make sure that the fragment shader is executed regardless of whether
per-fragment tests pass or not as the spec requires.
So far we have been doing this for images only, but we should apply the same
treatment to all side effectful scenarios. Suggested by Curro.
This is not strictly required for compliance with the original
ARB_shader_atomic_counters extension, it's only necessary to get the execution
semantics specified in GL4.2+ right.
v2:
- Mark active_fs_has_side_effects as constant. (Curro)
- Mention that this is only only necessary to get the execution semantics
specified in GL4.2+ right. (Curro)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Some drivers can disable the FS unit if there is nothing in the shader code
that writes to an output (i.e. color, depth, etc). Right now, mesa has
a function to check for atomic buffers and the i965 driver also checks for
images. Refactor this logic into a generic function that we can use for
any source of side effects in a fragment shader. Suggested by Jason.
v2:
- Use '_Shader', as suggested by Tapani, to fix the following CTS test:
ES31-CTS.shader_atomic_counters.advanced-usage-many-draw-calls2
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
The hardware provides us no decent way of getting at the number of input
vertices in the patch topology from the tessellation control shader.
It's actually very surprising - normally this sort of information would
be available in the thread payload.
For the precompile, we guess that the number of vertices will be the
same for both the input and output patches. This usually seems to be
the case.
On Gen8+, we could pass in an extra push constant containing this value.
We may be able to do that on Haswell too. It's quite a bit trickier on
Ivybridge, however.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
The TCS is the first tessellation shader stage, and the most
complicated. It has access to each of the control points in the input
patch, and computes a new output patch. There is one logical invocation
per output control point; all invocations run in parallel, and can
communicate by reading and writing output variables.
One of the main responsibilities of the TCS is to write the special
gl_TessLevelOuter[] and gl_TessLevelInner[] output variables which
control how much new geometry the hardware tessellation engine will
produce. Otherwise, it simply writes outputs that are passed along
to the TES.
We run in SIMD4x2 mode, handling two logical invocations per EU thread.
The hardware doesn't properly manage the dispatch mask for us; it always
initializes it to 0xFF. We wrap the whole program in an IF..ENDIF block
to handle an odd number of invocations, essentially falling back to
SIMD4x1 on the last thread.
v2: Update comments (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
The TES is essentially a post-tessellator VS, which has access to the
entire TCS output patch, and a special gl_TessCoord input. Otherwise,
they're very straightforward.
This patch implements SIMD8 tessellation evaluation shaders for Gen8+.
The tessellator can generate a lot of geometry, so operating in SIMD8
mode (8 vertices per thread) is more efficient than SIMD4x2 mode (only
2 vertices per thread). I have another patch which implements SIMD4x2
mode for older hardware (or via an environment variable override).
We currently handle all inputs via the pull model.
v2: Improve comments (suggested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This field is used as a flag to optimise out any varyings that don't have
a matching varying on the other side of the interface.
The value should be the same for all varyings (except for SSO but we can't
optimise those) by the time they reach nir and are no longer be needed.
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Also emits a method to properly bind the class to a subchannel, which
was missing previously. The kernel currently doesn't care, but this
will break if it ever decides to (ie. to support multiple sw classes).
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
The kernel previously exposed incorrect classes for some of the chipsets
that this code supports. It no longer does, but the older object ioctls
have compatibility to avoid breaking userspace.
This needs to be fixed before switching over to the newer interfaces.
Rather than hardcoding chipset->class like the rest of the driver does,
this makes use of (new) sclass queries to determine what's available.
v2.
- update to use symbolic class identifier from <nvif/class.h>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Switching to the newer libdrm entry-points tells libdrm that it's OK to
make use of newer kernel interfaces.
We want to be able to isolate any bugs to either the interfaces changes,
or the use of NVIF itself. As such, this commit has a slight hack which
forces libdrm to continue using the older kernel interfaces.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
The winsys layer would attempt to cleanup the nouveau_device if screen
init failed, however, in most paths the pipe driver would have already
destroyed it, resulting in accesses to freed memory etc.
This commit fixes the problem by allowing the winsys to detect whether
the pipe driver's destroy function needs to be called or not.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
If oViewport is written, vertex reuse need to be turned off.
If oViewport is constant, vertex reuse is fine, and VPORT_PROVOKE_DISABLE
need to be set. (we don't have enough info to program VPORT_PROVOKE).
Fixes: arb_viewport_array-render-viewport-2 and some CTS tests.
v2: drop vport provoke write, drop initial state writing this
on evergreen, only program it on evergreen.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
If oViewport is written, vertex reuse need to be turned off.
If oViewport is constant, vertex reuse is fine, and VPORT_PROVOKE_DISABLE
need to be set. (We don't know if oViewport is constant so we
skip this.)
Fixes: arb_viewport_array-render-viewport-2 and some CTS tests.
v2: drop writing to provoke disable, drop write in initial
state.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This function deals with vertex inputs and fragment
outputs, so we should count the attribute locations
correctly for the vertex inputs.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
I was cleverly using one iteration to obtain a pointer to the last item
in ralloc's singly list child list, while also setting parents.
Unfortunately, I forgot to set the parent on that last item.
Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This doubles the element width for the types that are greater
than 2 elements wide.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This doesn't apply to other stages. This is only
used in the mesa/st code, which needs further fixes.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This is a rewrite of vc4_opt_qpu_schedule.c to operate on QIR. Texture
fetch can probably take as much as the rest of the cycles of the program,
so it's important to hide our other cycles during it (which is hard to do
after register allocation). Also, we can queue up multiple texture
requests before collecting the resulting samples, so that we keep the
texture unit busy more of the time.
High-settings openarena performance +2.35849% +/- 0.221154% (n=7). Also
about 2-3% on the multiarb demo. 8 piglit tests
(ext_framebuffer_multisample accuracy depthstencil) go from failing in
rendering to failing in register allocation, but hopefully I can fix that
up with some better register pressure handling here.
total instructions in shared programs: 87723 -> 88448 (0.83%)
instructions in affected programs: 78411 -> 79136 (0.92%)
total estimated cycles in shared programs: 276583 -> 246306 (-10.95%)
estimated cycles in affected programs: 265691 -> 235414 (-11.40%)
There's only high latency between a complete texture fetch setup and
collecting its result, not between each step of setting up the texture
fetch request.
So vertex shader input attributes are handled different than internal
varyings between shader stages, dvec3 and dvec4 only count as
one slot for vertex attributes, but for internal varyings, they
count as 2.
This patch comments all the uses of this API to clarify what we
pass in, except one which needs further investigation
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
The old function didn't work for matrices, and we need this
in other places to fix some other problems, so move to a helper
in glsl type and fix the one user so far.
A dual slot double is one that has 3 or 4 components in it's
base type.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
