Commit Graph

20 Commits

Author SHA1 Message Date
Eric Anholt
2d17dbfb53 intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.

Fixes piglit fbo-clearmipmap.

Bug #23552. (automatic mipmap generation)
2009-10-23 14:12:24 -07:00
Eric Anholt
8f81a6468f intel: Avoid trying to do blits to Y tiled regions.
This is somewhat nasty, but we need to do Y-tiled depth for FBO support.
May help with corruption and hangs since enabling texture tiling, and
since switching depth textures to Y tiled.

Fixes piglit depthtex.c on 965.
2009-06-23 19:31:11 -07:00
Eric Anholt
246d59c29e intel: Fix some potential writes to zero-copy PBOs when used as regions.
I was in the midst of fixing some blitting-with-Y-tiled issues when I
noticed this.  Hopefully PBO usage will be a little more robust, as a
result.
2009-06-23 19:31:11 -07:00
Eric Anholt
6a49473ab5 intel: Remove long-unused intel_region_fill and intelEmitFillBlit. 2009-06-23 19:31:10 -07:00
Eric Anholt
1ba96651e1 intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off.  Thus, the texture_tiling driconf option defaults
off there for now.
2009-06-04 14:00:43 +00:00
Eric Anholt
40dd024be6 intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures.  The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.

Note that this means we require libdrm 2.4.5.
2009-02-21 10:53:41 -08:00
Brian Paul
ecadb51bbc mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template 2008-09-18 15:17:05 -06:00
Eric Anholt
8db761409d intel: Add a width field to regions, and use it for making miptrees in TFP.
Otherwise, we would use the pitch as width of the texture, and compiz would
render the pitch padding on the right hand side.
2008-09-12 15:48:13 -07:00
Eric Anholt
3628185f56 intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change. 2008-09-10 13:59:45 -07:00
Kristian Høgsberg
f56b569e9a DRI2: Drop sarea, implement swap buffers in the X server. 2008-08-29 12:13:14 -04:00
Dave Airlie
f75843a517 Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c.
2008-08-24 17:59:10 +10:00
Dave Airlie
7c81124d7c Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-24 17:52:40 +10:00
Eric Anholt
2e841880cf drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. 2008-07-11 18:58:19 -07:00
Kristian Høgsberg
c5c73c1b60 Hook up i915 driver to new DRI2 infrastructure. 2008-02-14 17:56:44 -05:00
Zou Nan hai
a9a483b43e [intel] use _mesa_copy_rect for upload compressed texture,
this fix bad texture issue in some games(UT and quake).
2008-02-01 17:36:56 +08:00
Eric Anholt
c5456a6b24 [intel] Remove useless intel_region_idle.
The idling it was trying to ensure was covered by the
intel_miptree_image_map()->intel_region_map() that immediately followed it.
2007-12-14 14:40:03 -08:00
Eric Anholt
7c71ef3a3d [intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes.  It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965).  The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-12 11:52:10 -08:00
Eric Anholt
f00a64999c [intel] Add 965 support to shared intel_blit.c
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16 17:29:30 -08:00
Eric Anholt
9b461d4d02 [i915] Pass static region names in so debugging says more than "static region". 2007-11-16 16:18:30 -08:00
Eric Anholt
77a5bcaff4 [intel] Move over files that will be shared with 965-fbo work. 2007-11-09 14:27:33 -08:00