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Author SHA1 Message Date
Sil Vilerino
b909058fdc d3d12: Add .clang_format file 
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
 2022-05-17 21:02:25 +00:00
Sil Vilerino
15dbf8f05a st_vdpau: Pass format when opening resource from handle in st_vdpau_resource_from_description 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
 2022-05-17 21:02:25 +00:00
Sil Vilerino
95b184f471 util/vl_vlc: Support compiling in C++ 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
 2022-05-17 21:02:24 +00:00
Sil Vilerino
b2b907f052 util/u_format: Drop assert that has valid/well-defined behavior 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
 2022-05-17 21:02:24 +00:00
Sil Vilerino
31dcb39615 gallium/vl: Add software winsys and offscreen winsys 
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
 2022-05-17 21:02:24 +00:00
Adam Jackson
68aa2099fa dri2: Require a loader with working buffer invalidation 
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10808>
 2022-05-17 20:31:50 +00:00
Adam Jackson
4d0179af32 glx/dri2: Require DRI2 >= 1.3 for working buffer invalidation 
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10808>
 2022-05-17 20:31:50 +00:00
Michel Zou
dc73de630e zink: fix pointer size conversion warning 
fixes:  34e62bfa

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16532>
 2022-05-17 20:20:52 +00:00
Lionel Landwerlin
9d0db8d4c4 intel/perf: deal with OA reports timestamp values on DG2 
OA reports on XeHP have their timestamp shifted to the left by 1. To
get that back in the same time domain as the REG_READ you need to
shift it back to the right and you're loosing the top bit.

v2: use ull for 64bit constant (Ian)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
773f41e3e4 intel/perf: disable sseu setting on Gfx12.5+ 
This is rejected by i915.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
d2834dd626 intel/perf: add new layout for Gfx12.5 products 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
66045acdf9 intel/perf: add max vfuncs 
New counters will use those from inside their read function to
generate percentage numbers.

v2: Forgot to update Iris (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
c740ca6000 intel/perf: add support new variable counting the number of EUs in slice0-3 
v2: MIN2(4, max_slices) (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
6f63bc38e7 intel/perf: add OA A counter type 
On Gfx12.5 products, we'll need to capture a couple of A counters that
are not captured in MI_RPC reports. Those are actually global,
previously all A counters were per context.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
376e420abb intel/perf: stop overriding oa_format 
This already set in the intel_perf_setup.h file at metric set
creation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
aa04b47c6e intel/perf: add support for GtSlice/GtSliceXDualsubsliceY variables 
For those, we'll fish the information out of the devinfo.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
d134a62345 intel/perf: add support for dualsubslice count variable 
This is the same as the subslice count.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
efc2782f97 intel/perf: store a copy of devinfo 
In the future we'll pull more information off devinfo.

v2: Constify pointers (Ian)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin
0df4b96062 intel/perf: add support for new opcodes in code generation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Chad Versace
fe3e850dfb venus: Don't encode ignored pTessellationState 
The spec says that VkGraphicsPipelineCreateInfo::pTessellationState is
ignored and may be an invalid pointer in some cases. When ignored,
patch the pCreateInfo with `pTessellationState = NULL`, so the encoder
doesn't attempt to encode an invalid pointer.

Tested in Borealis, with debug build of venus, with a minimal test app
that sets `.pTesselationState = 0x17`. Pre-patch, the app crashes;
post-patch, the app works.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16284>
 2022-05-17 19:47:52 +00:00
Chad Versace
683b6e8d35 venus: Refactor vn_fix_graphics_pipeline_create_info 
We currently do only a single fix. Prepare to do multiple independent
fixes.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16284>
 2022-05-17 19:47:52 +00:00
Dave Airlie
9c45b541e6 vl: fix codec checks to disable properly 
This was wrong and enabled codecs where they shouldn't have been.

Fixes: 7ab05e3c3f ("gallium/vl: respect the video codecs configure in meson")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16542>
 2022-05-17 19:17:38 +00:00
Dave Airlie
74976640b3 meson: add build-id to pipe libraries 
Without this the cache setup was crashing with CL and the dynamic
pipe libraries.

Reported and debugged on irc by consolers

Cc: mesa-stable
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16341>
 2022-05-17 18:50:54 +00:00
Gert Wollny
bbff12a191 r600/sb: Fall back to un-optimized shader if scheduling fails 
Sometimes the optimizer created codes that can't be scheduled,
instead of failing completely, simply bail out and use the
un-optimized code.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16499>
 2022-05-17 18:43:30 +00:00
Gert Wollny
d8e6abf542 r600/sb: Don't create three source ops with all kcache values 
There is a good chance that the created instruction can't be
scheduled, so avoid this case.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16499>
 2022-05-17 18:43:30 +00:00
Jason Ekstrand
d9048e31a0 radv: Use vk_image_view as the base for radv_image_view 
I've left the extent field because, even though it looks like it should
be roughly equivalent, it's weirdly different on different hardware and
I didn't want to mess with it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
c56f3dcbaa radv: Use vk_image as the base for radv_image 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
992690e483 radv: Only use PLANE_0 in meta when actually needed 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
fc8d2543fc vulkan,v3dv: Add a driver_internal flag to vk_image_view_init/create 
We already had a little workaround for v3dv where, for some if its meta
ops, it had to bind a depth/stenicil image as color.  Instead of
special-casing binding depth/stencil as color, let's flip on the
drier_internal flag and get rid of most of the checks in that case.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
ae2ca1d2ac v3dv: Drop the region temporary from blit_shader 
We're no longer stomping aspects, so there's no need.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
f99ac7f2de v3dv: Don't use color aspects for depth/stencil images 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
36e0f9507d vulkan: Only be clever about vk_image_view::view_format for normal views 
For color view of depth views, just set whatever format they asked for.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Jason Ekstrand
f5e1b06622 v3dv: Add a create_image_view helper for internal views 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Samuel Pitoiset
8510d5daa3 aco: use ac_is_llvm_processor_supported() for checking LLVM asm support 
It seems more universal but it's needed to create a temporary TM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16494>
 2022-05-17 17:14:21 +00:00
Samuel Pitoiset
07eba9a15a radv: do not lower loading TESS/ESGS rings using the ABI for LLVM 
LLVM uses an implicit argument for the ring offsets and this lowering
was just broken.

This fixes tessellation and geometry on all generations with LLVM.

Fixes: 896a55f47d ("radv: Lower ABI in NIR for tess/ESGS/NGG shader arguments.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16530>
 2022-05-17 16:45:02 +00:00
Alyssa Rosenzweig
6b1e73c700 asahi: Fix hangs waiting on the notification queue 
Dequeue and WaitForAvailableData can race. Restructure the loop to avoid
this. Fixes all timeouts in dEQP.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16518>
 2022-05-17 15:00:15 +00:00
Emma Anholt
81bded100c i915g/ci: Add depth-clear-precision-check xfails like everyone else. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:07:35 -07:00
Emma Anholt
0220348250 ci/crocus: Merge the piglit runs with the deqp runs. 
Fewer manual buttons to click.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:05:01 -07:00
Emma Anholt
725f56fdb6 ci/crocus: Manual CI updates after CI was down for a bit. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:05:01 -07:00
Konstantin Seurer
b9f43059fc Revert "radv: Make fill_buffer_shader non-static" 
We do not need this any longer since
radv_acceleration_structure.c uses
radv_fill_buffer now instead.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
 2022-05-17 13:10:07 +00:00
Konstantin Seurer
405b2bb79c radv: Use radv_fill_buffer for accel struct builds 
It turns out, that the fuchsia sort may actually
perform clears with size < 16 which hits an assert
in radv_fill_buffer_shader. This fixes random
crashes in Control.

Fixes: be57b08 ("radv: Build accaleration structures using LBVH")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
 2022-05-17 13:10:07 +00:00
Konstantin Seurer
183c15dbb2 radv: Allow radv_fill_buffer to work with VAs only 
Makes the bo parameter optional which is useful
for the clears performed by acceleration structure
build commands.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
 2022-05-17 13:10:07 +00:00
Marek Olšák
61d5594064 Revert "mesa: consider the sample count when choosing a texture format" 
This reverts commit 89c94502b6.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16524>
 2022-05-17 11:47:42 +00:00
Marek Olšák
265c9af69e Revert "frontend/dri: allow swapped BGR->RGB channel order for MSAA color buffers" 
This reverts commit cfec9a55ea.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16524>
 2022-05-17 11:47:42 +00:00
Marek Olšák
ad50daa982 radeonsi: fix resource_copy_region with ETC formats (e.g. for Stoney) 
Only Stoney, Vega10, Raven, and Raven2 support ETC.

Fixed tests:
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16ui.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16ui.texture2d_to_texture2d

Fixes: cf1e562fdd - radeonsi: remove compressed and subsampled gfx copy from resource_copy_region
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6431

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16491>
 2022-05-17 11:26:25 +00:00
Dave Airlie
0a056f84ed llvmpipe: align scratch size to 64-bit size. 
This fixes a crash with luxmark where it uses a 12-byte scratch space,
but when llvmpipe allocates it for 8 lanes, it isn't properly aligned
for 64-bit.

Karol found this debugging rusticl.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16288>
 2022-05-17 11:00:03 +00:00
Marek Olšák
394e42427f winsys/amdgpu: initialize IB_PREAMBLE in advance 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
1fdc3b0fde radeonsi: move CS preamble emission into the winsys 
The preamble will be skipped by the kernel if there is no context switch.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
32c7805ccc radeonsi: merge all preamble states into one 
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.

The preamble will be passed to the kernel as an IB to execute on a context
switch only.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
f46cd73e29 radeonsi/gfx11: optimize attribute stores 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00