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Author SHA1 Message Date
Alyssa Rosenzweig
7bfaa119f4 pan/bi: Lift split/collect cache from AGX 
Design based on ACO (and fruitful discussions with Daniel).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
8fdb01b96f pan/bi: Create COLLECT during isel 
This transitions us away from the fake SSA we currently use for vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
5c0977d230 pan/bi: Expand MAX_DESTS to 4 
For splits.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
9924e6f291 pan/bi: Fix mov and pack_32_2x16 
Move can take in a vector and write a scalar, depending on the swizzle. We need
to handle this case. Split out mov and pack_32_2x16 so we can specify correct
behaviour for both. Also drop unused 1-bit boolean stuff which obscured the fix.

Fixes: 76cea8e27b ("panfrost: Fix pack_32_2x16 implementation")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
bc17288697 pan/bi: Lower split/collect before RA 
For transitioning to the new scalarized IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
0c7f126277 pan/bi: Add bi_before_block cursor 
Useful for preloading.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
298d20f805 pan/bi: Add collect and split instructions 
These move-like instructions will be generated during instruction selection and
lowered before/after register allocation.

These need special printer support until we get dynamic sources/destinations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
afd88d1380 pan/bi: Add source/destination counts 
In preparation for dynamic allocation, as needed for phi nodes and parallel
copies. For now, it just serves to simplify the semantics of splits and
collects.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
0523b6b89b pan/bi: Use value-based interference with LCRA 
"Revisiting Out-of-SSA Translation for Correctness, Code Quality, and
Efficiency" discusses "value-based interference": two variables interfere if and
only if there exists a point in the program where they are both live *with
different values*. In particular, the source and destination of a move do not
interfere a priori, because they have the same value at that point in the
program. (If a later instruction overwrites one, the required interference will
be added there).

We can use this idea to avoid some extra interferences, avoiding a regression in
moves from split/collect.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
896dc63623 pan/bi: Lower phis to scalar 
If we don't lower phis to scalar, when we go out of SSA, we can get vector
nir_registers. In particular, we can get code like:

   r0 = vec2 r0.y, r0.x

This code looks like a move, but is in fact a swap. The trivial lowering of vec2
would not work -- the following fails to swap correctly:

   r0.x = r0.y
   r0.y = r0.x

Currently, we generate temporaries to handle these cases. It's easy to move the
complexity to NIR, though, and we'll want to scalarize phis for SSA-based RA
anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
c8882ee115 pan/bi: +JUMP can't read same-cycle temp 
Minor ISA detail missed in the Bifrost scheduler. I hit this in an early version
of this series (where a move feeding into a blend shader return was not
coalesced). Let's get it fixed in the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
c387096eca pan/va: Use 64-bit lowering for texturing 
Texture instructions on Valhall take 64-bit sources. Now that we have
infrastructure to handle this properly, we don't need to use a non-SSA node to
hack around the optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
89a3746bc1 pan/va: Lower split 64-bit sources 
This ensures Valhall 64-bit constraints are respected in a simple way. It's not
the most efficient, though. Optimization is deferred until full Valhall support
is upstreamed and the RA is overhauled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
65839d8c3c pan/va: Mark more source sizes 
This source size information will be consumed by the 64-bit lowering pass, so
ensure it's accurate. That means marking 32-bit and 64-bit sources explicitly on
message passing where it wouldn't match up with the type size suffix of the
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
04a1df8c65 pan/bi: Update bi_count_write_registers for Valhall 
We add some new instructions on Valhall with special register requirements
(texturing, atomics). Handle these appropriately so we can do RA on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Jason Ekstrand
8b13ee75ba vulkan: Fall back to raw data objects when deserializing if ops == NULL 
This can happen if an object is serialized whose object type isn't in
the pipeline cache import ops.  In this case, we generate a raw data
object and plan to turn it into the right object type later.

Fixes: d35e78bb85 ("vulkan/pipeline_cache: Implement deserialize for raw objects")
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16584>
 2022-05-19 14:51:40 +00:00
Rhys Perry
1e710f7a2c radv: validate shaders after linking passes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
75c80be484 radv: add missing NIR_PASS() and switch from NIR_PASS_V() 
Unlike NIR_PASS_V(), NIR_PASS() can skip printing the shader when
NIR_DEBUG=print.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
d98b7817fc radv: call nir_metadata_preserve in various lowering passes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
6087f1951e nir: call nir_metadata_preserve in nir_lower_memory_model 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
3eed871f41 nir: call nir_metadata_preserve in nir_vectorize_tess_levels 
This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
f10d4bf963 nir: call nir_metadata_preserve in nir_io_add_const_offset_to_base 
This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
0d9ead8ca2 nir: print file when validation fails 
This should make it clear whether a validation failure happens in RADV or
zink.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Rhys Perry
836470d433 nir: allow NIR_PASS(_, ) 
If a user wants to skip printing the shader if no changes were made
without declaring a dummy variable for the progress.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>
 2022-05-19 13:37:20 +00:00
Pierre-Eric Pelloux-Prayer
cf9ee6d432 radeonsi: wait for PS idle in si_set_framebuffer_state 
This is needed to avoid write-after-read hazards in
texture -> render transitions.

This fixes fbo-depth tests that were flaky on GPUs (at
least sienna_cichlid and vega20).

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16561>
 2022-05-19 12:22:11 +00:00
Marek Olšák
2443054932 amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
 2022-05-19 11:55:50 +00:00
Indrajit Kumar Das
c6bb8961a8 mesa/st: clear color buffers using color from a constant buffer 
v2: fixed GLCTS failures (mareko)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>
 2022-05-19 11:18:31 +00:00
Indrajit Kumar Das
2204bf509d mesa/st: add nir shader to clear color buffers using constant value 
v2: use load_uniform instead of load_ubo to fix vc4

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>
 2022-05-19 11:18:30 +00:00
Indrajit Kumar Das
773a23eb6d gallium/u_blitter: clear color buffers using color from a constant buffer 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>
 2022-05-19 11:18:30 +00:00
Indrajit Kumar Das
03bc7503d4 radeonsi: save the fs constant buffer to the util blitter context 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>
 2022-05-19 11:18:30 +00:00
Tomeu Vizoso
0d8cbf551d Revert "ci: Disable jobs to the Collabora lab" 
This reverts commit 224544dc33.

Work has finished and the lab is up and running.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16600>
 2022-05-19 09:31:26 +00:00
Danylo Piliaiev
850ae76970 util/u_trace: Add json output 
If we want to load the u_trace output somewhere for analysis it's much
easier to deal with json than to parse strings.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16475>
 2022-05-19 07:41:45 +00:00
Samuel Pitoiset
0c8a07f25d aco: remove unnecessary intrinsics that are lowered at the ABI level 
Fixes: f553076eaf ("aco: Remove now-superfluous intrinsics.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16577>
 2022-05-19 06:49:07 +00:00
Filip Gawin
fb2426db7a r300: keep negation if w is an inline constant 
(in dataflow swizzles pass)

helps with:
dEQP-GLES2.functional.shaders.random.conditionals.combined.73
on r300 and r400

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16559>
 2022-05-19 06:34:02 +00:00
Timothy Arceri
c4cec84231 nir/i915g/r300/nv30: skip marking varyings as flat in some drivers 
Some older drivers don't support GLSL versions with the concept of flat
varyings and also don't support integers. Here we add a new setting to
make sure we don't use the optimisation that sets varyings to flat.
This setting helps us avoid marking varyings as flat and therefore
potentially having them changed to ints via varying packing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6500
Fixes: 7647023f3b ("glsl: enable the use of the nir based varying linker")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16573>
 2022-05-19 01:05:32 +00:00
Jason Ekstrand
2f38adda63 v3dv: Loosen an assert in copy_buffer_to_image_shader 
In f99ac7f2de ("v3dv: Don't use color aspects for depth/stencil
images"), we stopped using color aspects for depth/stencil images in a
bunch of cases.  This causes us to trigger an assert in
copy_buffer_to_image_shader where it assumes 16-bit is always color but
now it can also be D16_UNORM.  The assert isn't protecting us from
anything we weren't already doing before so we can just loosen it a bit.

Fixes: f99ac7f2de ("v3dv: Don't use color aspects for depth/stencil images")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16592>
 2022-05-19 00:06:21 +00:00
Emma Anholt
f5e714cbf9 ci/crosvm: Terminate the previous crosvm after a deqp-runner timeout. 
When deqp-runner times out, it kills the deqp process, which in our case
is the previous invocation of our shell script, so the crosvm and socat
cleanup never happened.  crosvm has a way to cleanly shut down a previous
crosvm invocation, so let's just use that and do our cleanup when we need
to.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>
 2022-05-18 22:49:20 +00:00
Emma Anholt
b82f920384 ci/crosvm: Rename VSOCK_TEMP_DIR -> VM_TEMP_DIR. 
It doesn't contain anything about the vsocks, just files shared between
the host and the guest.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>
 2022-05-18 22:49:20 +00:00
Emma Anholt
b836cd937c ci/crosvm: Simplify the CID setup. 
Now that deqp-runner tells us which thread we are, we don't need to go
probing for a spare directory to use.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>
 2022-05-18 22:49:20 +00:00
Jesse Natalie
be5c7c0351 dzn: Add new parameter to vk_image_view_init call 
Fixes: fc8d2543 ("vulkan,v3dv: Add a driver_internal flag to vk_image_view_init/create")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16589>
 2022-05-18 11:03:26 -07:00
Jesse Natalie
29a8f1f03b d3d12: MSVC warning around operator precedence causing uint32_t==bool 
Fixes: b171a6ba ("d3d12: Add video encode implementation of pipe_video_codec")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>
 2022-05-18 09:28:49 -07:00
Jesse Natalie
4b34869d9d d3d12: Don't use VLAs 
Fixes: 739283da ("d3d12: Improve planar resource support to handle video requirements")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>
 2022-05-18 09:28:47 -07:00
Jesse Natalie
9e9c8df3f0 d3d12: Include windows.h on Windows before dxgicommon.h 
The dxgicommon.h header uses UINT types without including windows.h itself.

Fixes: 6dbe05ff ("d3d12: Add util video functions to d3d12_format")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>
 2022-05-18 09:28:30 -07:00
Samuel Pitoiset
8396df5ad9 radv: init states from pRasterizationState at only one place 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>
 2022-05-18 13:53:35 +00:00
Samuel Pitoiset
7f08fe0b9f radv: init states from pViewportState at only one place 
Except the viewport/scissor arrays to avoid useless array copies.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>
 2022-05-18 13:53:35 +00:00
Samuel Pitoiset
f13b30fe62 radv: init states from pTessellationState at only one place 
It's part of the pre-rasterization state of graphics pipeline libs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>
 2022-05-18 13:53:35 +00:00
Connor Abbott
9f67fa368e tu: Implement VK_EXT_pipeline_creation_cache_control 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>
 2022-05-18 13:14:55 +00:00
Connor Abbott
49827da6fa tu: Implement VK_EXT_pipeline_creation_feedback 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>
 2022-05-18 13:14:55 +00:00
Connor Abbott
e348f2fb38 tu: Zero-initialize compute driver key 
Fixes: 05329d7 ("tu: Implement pipeline caching with shared Vulkan cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>
 2022-05-18 13:14:55 +00:00
Vadym Shovkoplias
33412e0231 drirc: Set limit_trig_input_range option for glmark2 
This fixes jellyfish rendering issues in glmark2 on Intel.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6479
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16525>
 2022-05-18 12:41:59 +00:00