Commit Graph

8 Commits

Author SHA1 Message Date
Kristian Høgsberg Kristensen
2b29342fae anv: Store prog data in pipeline cache stream
We have to keep it there for the cache to work, so let's not have an
extra copy in struct anv_pipeline too.
2016-03-05 13:50:07 -08:00
Jason Ekstrand
9a90176d48 anv/pipeline: Calculate the correct max_source_attr for 3DSTATE_SBE 2016-03-05 09:59:28 -08:00
Jason Ekstrand
38f4c11c2f anv/pipeline: Pull 3DSTATE_SBE into a shared helper 2016-03-01 08:46:32 -08:00
Jordan Justen
72efb68d48 anv/pipeline: Set URB offset to zero if size is zero
After 3ecd357d81, it may be possible for
the VS to get assigned all of the URB space.

On Ivy Bridge, this will cause the offset for the other stages to be
16, which cannot be packed into the ConstantBufferOffset field of
3DSTATE_PUSH_CONSTANT_ALLOC_*.

Instead we can set the offset to zero if the stage size is zero.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-28 10:51:38 -08:00
Kenneth Graunke
7f9b03cc8b anv: Emit 3DSTATE_PUSH_CONSTANT_ALLOC_* via a loop.
Now we're emitting HS and DS packets as well.
2016-02-24 11:13:08 -08:00
Kenneth Graunke
1024a66fc4 anv: Emit 3DSTATE_URB_* via a loop.
Rather than keeping separate {vs,hs,ds,gs}_start fields, we now store an
array indexed by the shader stage (MESA_SHADER_*).  The 3DSTATE_URB_*
commands are also sequentially numbered.  This makes it easy to just
emit them in a loop.

This simplifies the code a little, and also will make it easier to add
more credible HS and DS code later.
2016-02-24 11:13:02 -08:00
Jason Ekstrand
371b4a5b33 anv: Switch over to the macros in genxml 2016-02-20 09:09:28 -08:00
Jason Ekstrand
9851c8285f Move the intel vulkan driver to src/intel/vulkan 2016-02-18 10:37:59 -08:00