Commit Graph

96693 Commits

Author SHA1 Message Date
Marek Olšák
ed880fe192 gallium/u_inlines: improve pipe_reference_described perf for debug builds
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-09-10 14:53:01 -04:00
Marek Olšák
c042a34b14 gallium/auxiliary: don't dereference counters twice needlessly
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-09-10 14:52:32 -04:00
Marek Olšák
61767c059e gallium/u_inlines: normalize naming, use dst & src, style fixes (v2)
v2: update comments

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-09-10 14:52:32 -04:00
Marek Olšák
9f1bbbdbbd util: try to fix the Android and MacOS build
Bionic does not have pthread_setaffinity_np.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107869
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-09-10 14:49:07 -04:00
Jason Ekstrand
6f00785765 anv: Support v3 of VK_EXT_vertex_attribute_divisor
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-10 13:45:32 -05:00
Jason Ekstrand
34a17a48d4 vulkan: Update the XML and headers to 1.1.84
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-10 13:30:21 -05:00
Sergii Romantsov
bbe551f3ea mesa/meson: 32bit xmlconfig linkage
Building of 32bit mesa with meson causes linkage issue:
"undefined reference to `util_get_process_name'"
Fixed by adding link-with mesa_util for xmlconfig primary.

v2: Removed '[]', commit message corrected.

v3: Reverted changes in gbm and glx libraries.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes: 2e1e6511f7 "util: extract get_process_name from xmlconfig.c"
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-09-10 08:57:42 -07:00
Jose Fonseca
52ca32121b Require Visual Studio 2015.
We no longer need or use Visual Studio 2013.

https://ci.appveyor.com/project/jrfonseca/mesa/build/52

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-09-10 10:10:16 +01:00
Jose Fonseca
d5f934522d util: Make util_context_thread_changed a no-op on Windows.
Spite using thrd_t types, these functions are wed to pthreads, and break
Windows builds, because thrd_current() is not implemented there, as it's
impossible to have an efficient thrd_current() implementation on
Windows.

Trivial.
2018-09-10 10:10:16 +01:00
Erik Faye-Lund
c4017106bb virgl: do not map zero-sized resource
When creating textures, we avoid creating backing-store for all
multisampled textures, not just depth buffers.

So we can't try to map them later. That's just going to fail. So
let's take the blit-based code-path that seems to avoid this problem.

This make this piglit test-case no longer crash (although it still
fails):

bin/copyteximage 2D -samples=2 -auto

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-10 10:35:42 +02:00
Erik Faye-Lund
8083464013 virgl: remove dead code
We don't use the size we calculate in this function, so let's just
drop the calculation

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-10 10:35:32 +02:00
Erik Faye-Lund
b9c40e492d virgl: drop needless return-code
We always return TRUE, and we never check the return-value. Let's
just drop the return value instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-10 10:35:20 +02:00
Erik Faye-Lund
9635869d73 virgl: free trans on map-error
When we fail to map memory, we should also free trans to avoid
leaking memory.

Noticed while reading code.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-10 10:35:02 +02:00
Chris Wilson
44e3e6a9b4 i965: Bump aperture tracking to u64
As a prelude to handling large address spaces, first allow ourselves the
luxury of handling the full 4G.

Reported-by: Andrey Simiklit <asimiklit.work@gmail.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-10 09:14:46 +01:00
Mathias Fröhlich
2fece204c0 etnaviv: Reduce max offset to available hardware bits.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-09-10 07:59:31 +02:00
Mathias Fröhlich
4569bc6ad0 gallium: New cap PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET.
Introduce a new capability for the maximum value of
pipe_vertex_element::src_offset. Initially just every driver
backend returns the value previously set from _mesa_init_constants.
So this shall end up in no functional change.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2018-09-10 07:59:31 +02:00
Dave Airlie
240af61494 virgl: don't send a shader create with no data. (v2)
This fixes the situation where we'd send a shader with just the
header and no data.

piglit/glsl-max-varyings test was causing this to happen, and
the renderer fix was breaking it.

v2: drop fprintf

Fixes: a8987b88ff "virgl: add driver for virtio-gpu 3D (v2)"
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2018-09-10 12:23:30 +10:00
Timothy Arceri
14fe9fa11b mesa: enable ARB_vertex_buffer_object in core profile
This extension is required by "Wolfenstein: The Old Blood"
and is exposed in core in the Nvidia binary driver.

All the functions are just alias of the core functions so
there should be nothing more to do.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-09-08 14:35:09 +10:00
Marek Olšák
21ca322e63 st/mesa: throttle texture uploads if their memory usage goes beyond a limit
This prevents radeonsi from running out of memory. It also increases
texture upload performance by being nice to the kernel memory manager.
2018-09-07 17:59:02 -04:00
Marek Olšák
9ce2cef68f gallium: add PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET 2018-09-07 17:59:02 -04:00
Marek Olšák
7ac52c2e38 Revert "gallium/os_thread: simplify helper pipe_current_thread_get_time_nano"
This reverts commit 6d477bc546.

It fixes the Windows build hopefully.
2018-09-07 16:52:36 -04:00
Jason Ekstrand
465e5a868c anv: Clamp scissors to the framebuffer boundary
The Vulkan 1.1.81 spec says:

    "It is legal for offset.x + extent.width or offset.y + extent.height
    to exceed the dimensions of the framebuffer - the scissor test still
    applies as defined above. Rasterization does not produce fragments
    outside of the framebuffer, so such fragments never have the scissor
    test performed on them."

Elsewhere, the Vulkan 1.1.81 spec says:

    "The application must ensure (using scissor if necessary) that all
    rendering is contained within the render area, otherwise the pixels
    outside of the render area become undefined and shader side effects
    may occur for fragments outside the render area. The render area
    must be contained within the framebuffer dimensions."

Unfortunately, there's some room for interpretation here as to what the
consequences are of having the render area set to exactly the
framebuffer dimensions and having a scissor that is larger than the
framebuffer.  Given that GL and other APIs provide automatic clipping to
the framebuffer, it makes sense that applications would assume that
Vulkan does this as well.  It costs us very little to play it safe and
just clamp client-provided scissors to the framebuffer dimensions.
Fortunately, the user is required to provide us with at least one
scissor so we don't need to handle the case where they don't.

Fixes: fb2a5ceb32 "anv: Emit DRAWING_RECTANGLE once at driver..."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
b08b4b2b25 anv: Disable the vertex cache when tessellating on SKL GT4
I have no idea if I'm correct about what's going wrong or if this is the
correct fix.  However, in my multiple weeks of banging my head on this
hang, a VUE reference counting bug seems to match all the symptoms and
it definitely fixes the hang.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107280
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
5dee89438a anv: Implement a VF cache invalidate workaround
Known to fix nothing whatsoever but it's in the docs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
c643c5e18d anv: Re-emit vertex buffers when the pipeline changes
Some of the bits of VERTEX_BUFFER_STATE such as access type, instance
data step rate, and pitch come from the pipeline.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Marek Olšák
25ffb84016 radeonsi: pin the winsys thread to the requested L3 cache (v2)
v2: rebase

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 16:03:36 -04:00
Marek Olšák
8016639f63 gallium/u_threaded: implement set_context_param for thread pinning (v2)
v2: - use set_context_param
    - set set_context_param even if the driver doesn't implement it

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 16:03:36 -04:00
Marek Olšák
8d473f555a st/mesa: pin driver threads to a specific L3 cache on AMD Zen (v2)
v2: use set_context_param

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 16:03:30 -04:00
Marek Olšák
e5e3b5cdcc gallium: add pipe_context::set_context_param for tuning perf on AMD Zen (v2)
State trackers will not use the new param directly, but will instead use
a helper in MakeCurrent that does the right thing.

v2: rework the interface

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 15:48:31 -04:00
Marek Olšák
6d477bc546 gallium/os_thread: simplify helper pipe_current_thread_get_time_nano
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 15:48:31 -04:00
Marek Olšák
15fa2c5e35 gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 15:48:31 -04:00
Marek Olšák
ce432e259d gallium/u_cpu_detect: fix parsing the CPU family
According to:
https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf

Also Intel:
https://www.microbe.cz/docs/CPUID.pdf

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 15:48:31 -04:00
Marek Olšák
a84fd58f48 gallium/u_cpu_detect: fix a race condition on initialization
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-07 15:48:31 -04:00
Dylan Baker
8396043f30 Replace uses of _mesa_bitcount with util_bitcount
and _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem
in nir for platforms that don't have popcount or popcountll, such as
32bit msvc.

v2: - Fix additional uses of _mesa_bitcount added after this was
      originally written

Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-09-07 10:21:26 -07:00
Dylan Baker
80825abb5d move u_math to src/util
Currently we have two sets of functions for bit counts, one in gallium
and one in core mesa. The ones in core mesa are header only in many
cases, since they reduce to "#define _mesa_bitcount popcount", but they
provide a fallback implementation. This is important because 32bit msvc
doesn't have popcountll, just popcount; so when nir (for example)
includes the core mesa header it doesn't (and shouldn't) link with core
mesa. To fix this we'll promote the version out of gallium util, then
replace the core mesa uses with the util version, since nir (and other
non-core mesa users) can and do link with mesautils.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-09-07 10:21:26 -07:00
Jason Ekstrand
f9e630e23d i965: Workaround the gen9 hw astc5x5 sampler bug
gen9 hardware has a bug in the sampler cache that can cause GPU hangs
whenever an texture with aux compression enabled is in the sampler cache
together with an ASTC5x5 texture.  Because we can't control what the
client binds at any given time, we have two options: resolve the CCS or
decompresss the ASTC.  Doing a CCS or HiZ resolve is far less drastic
and will likely have a smaller performance impact.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-09-07 10:42:40 -05:00
Eric Anholt
a91b158bd9 v3d: Fix setup of the VCM cache size.
There were two bugs working together to make things mostly work: I wasn't
dividing the VPM output size available by the size of a batch (vertex),
but I also had the size of the VPM reduced by a factor of 8.

Fixes dEQP-GLES3.functional.vertex_array_objects.all_attributes and it
seems also my intermittent varying failures.

Fixes: 1561e4984e ("v3d: Emit the VCM_CACHE_SIZE packet.")
2018-09-07 08:11:38 -07:00
Eric Anholt
f73f748323 v3d: Fix SRC_ALPHA_SATURATE blending for RTs without alpha.
Fixes
dEQP-GLES3.functional.fragment_ops.blend.default_framebuffer.rgb_func_alpha_func.dst.src_alpha_saturate_src_alpha_saturate
and friends with --deqp-egl-config-name=rgb565d0s0

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
2018-09-07 08:11:05 -07:00
Lionel Landwerlin
69874e9a6a intel/genxml: turn SLM Enable bit into boolean
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-07 14:46:20 +01:00
Sergii Romantsov
97fcccb25e i965/tools: 32bit compilation with meson
Building of 32bit mesa with meson causes issue:
"implicit declaration of function ‘__builtin_ia32_clflush’".
Fixed by adding msse2 compilation flag.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes: 314879f7fe (i965: Fix asynchronous mappings on !LLC platforms.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-07 13:46:48 +01:00
Sergii Romantsov
d709f12792 intel: compiler option msse2 and mstackrealign
Seems in case of 32-bit library, usage of msse2 makes
some stack corruption or incorrect instructions.
Usage with mstackrealign fixes that case.

v2: Fixed meson.

v3: Definition of c_sse2_args moved on the top (L.Landwerlin).
    Added mstackrealign for Android's mks where msee4.1 is used.

v4: Added for Vulkan also.

v5: Commit message correction.

CC: <mesa-stable@lists.freedesktop.org>
Fixes: 6b05c080f2 (i965: Compile with -msse3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-07 13:45:46 +01:00
Rob Clark
5404e0637f freedreno: fix rast->depth_cleap_near/far
Fixes: daa19363de gallium: split depth_clip into depth_clip_near & depth_clip_far
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-07 07:41:43 -04:00
Marek Olšák
fda7683726 gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi 2018-09-06 21:53:00 -04:00
Marek Olšák
daa19363de gallium: split depth_clip into depth_clip_near & depth_clip_far
for AMD_depth_clamp_separate.
2018-09-06 21:53:00 -04:00
Jason Ekstrand
7b26741806 anv/pipeline: Only consider double elements which actually exist
The brw_vs_prog_data::double_inputs_read field comes directly from
shader_info::double_inputs which may contain inputs which are not
actually read.  Instead of using it directly, AND it with inputs_read
which is only things which are read.  Otherwise, we may end up
subtracting too many elements when computing elem_count.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103241
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-06 16:07:50 -05:00
Jason Ekstrand
44ec31cd75 nir: Drop the vs_inputs_dual_locations option
It was very inconsistently handled; the only things that made use of it
were glsl_to_nir, glspirv, and nir_gather_info.  In particular,
nir_lower_io completely ignored it so anyone using nir_lower_io on
64-bit vertex attributes was going to be in for a shock.  Also, as of
the previous commit, it's set by every driver that supports 64-bit
vertex attributes.  There's no longer any reason to have it be an option
so let's just delete it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-06 16:07:50 -05:00
Jason Ekstrand
0909a57b63 radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remap
We were going out of our way to disable dual-location re-mapping in NIR
only to then do the remapping in st_glsl_to_nir.cpp.  Presumably, this
was so that double_inputs would be correct for the core state tracker.
However, now that we've it to gl_program::DualSlotInputs which is
unaffected by NIR lowering, we can let NIR lower things for us.  The one
tricky bit here is that we have to remap the inputs_read bitfield back
to the single-slot convention for the gallium state tracker to use.

Since radeonsi is the only NIR-capable gallium driver that also supports
GL_ARB_vertex_attrib_64bit, we only have to worry about radeonsi when
making core gallium state tracker changes.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-06 16:07:50 -05:00
Jason Ekstrand
25efd787cf compiler: Move double_inputs to gl_program::DualSlotInputs
Previously, we had two field in shader_info: double_inputs_read and
double_inputs.  Presumably, the one was for all double inputs that are
read and the other is all that exist.  However, because nir_gather_info
regenerates these two values, there is a possibility, if a variable gets
deleted, that the value of double_inputs could change over time.  This
is a problem because double_inputs is used to remap the input locations
to a two-slot-per-dvec3/4 scheme for i965.  If that mapping were to
change between glsl_to_nir and back-end state setup, we would fall over
when trying to map the NIR outputs back onto the GL location space.

This commit changes the way slot re-mapping works.  Instead of the
double_inputs field in shader_info, it adds a DualSlotInputs bitfield to
gl_program.  By having it in gl_program, we more easily guarantee that
NIR passes won't touch it after it's been set.  It also makes more sense
to put it in a GL data structure since it's really a mapping from GL
slots to back-end and/or NIR slots and not really a NIR shader thing.

Tested-by: Alejandro Piñeiro <apinheiro@igalia.com> (ARB_gl_spirv tests)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-06 16:07:50 -05:00
Marek Olšák
1285f71d3e gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-09-06 16:07:40 -04:00
Andrii Simiklit
2930b76cfe mesa/util: add missing va_end() after va_copy()
MSDN:
"va_end must be called on each argument list that's initialized
 with va_start or va_copy before the function returns."

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107810
Fixes: c6267ebd6c "gallium/util: Stop bundling our snprintf implementation."
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
2018-09-06 17:33:27 +01:00