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100 Commits

Author SHA1 Message Date
Marek Olšák
29965f356b ac: replace 5 ac_shader_abi::load_* callbacks with 1 intrinsic_load callback 
This merges them into si_llvm_load_intrinsic and reuses load_tess_varyings.

RADV only implemented 1 callback.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:45:31 -04:00
Marek Olšák
535d954914 radeonsi: try to group stage-specific code in si_llvm_translate_nir 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:45:31 -04:00
Marek Olšák
2b7906ea74 radeonsi: get rid of the ambiguous "prologue" word 
It has nothing to do with our "prolog" shader parts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:45:31 -04:00
Marek Olšák
4118717cba radeonsi: cleanups getting rid of the ambigous "epilogue" word 
It has nothing to do with our "epilog" shader parts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:44:57 -04:00
Marek Olšák
dc81f0ba46 ac/llvm: remove ac_shader_abi::emit_outputs 
it's called last in ac_nir_translate, so call it in the caller.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:44:57 -04:00
Marek Olšák
9a8413aaea radeonsi: inline si_nir_build_llvm 
it always returns true

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
 2022-05-13 06:44:57 -04:00
Marek Olšák
2a1c711052 ac/llvm: skip s_barrier if tess patches don't cross a wave boundary 
If tess patches are wholly in one wave, "s_waitcnt lgkm(0)" is sufficient.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
 2022-05-13 09:15:20 +00:00
Marek Olšák
59673001c8 radeonsi: add si_get_tcs_epilog_key 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
 2022-05-13 09:15:20 +00:00
Marek Olšák
20bb85e2ec ac/llvm: fix the remaining s_barriers for LLVM 15 
LLVM 15 doesn't insert s_waitcnt before barriers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
 2022-05-13 09:15:20 +00:00
Marek Olšák
e4882d6b7e ac/llvm: add gl_shader_stage parameter into ac_build_s_barrier 
this will be used later

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
 2022-05-13 09:15:20 +00:00
Marek Olšák
8d4c0197c3 radeonsi: wait before s_barrier in TCS epilog to fix LLVM 15 
Only LGKM is needed here.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
 2022-05-13 09:15:20 +00:00
Pierre-Eric Pelloux-Prayer
38e8a73e14 radeonsi: implement GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB in shaders 
Statistics only work in non-NGG mode. If screen->use_ngg is true, we can't
know if the draw will actually use NGG or not, so this commit switch
to a shader based implementation of this counter.

To avoid modifying si_query, the shader implementation behaves like the hw
one: it uses the same buffer size and offset.

The emulation path activation in the shader is controlled by vs_state_bit[31].

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
 2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer
529f316d87 radeonsi: fix VS kill_outputs handling 
981bd8cbe2 moved outputs removing handling to NIR, but instead of
applying it only to the last stage before the FS this now applies
it to both the GS and the VS.

This commit fixes this by clearing the kill_outputs field for
the VS when using a ES-GS shader.

Fixes: 981bd8cbe2 ("radeonsi: apply key.ge.opt.kill_{outputs,pointsize,clipdistance} in NIR")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16249>
 2022-05-02 13:41:39 +02:00
Marek Olšák
c888e77dfc ac/llvm: remove inst_offset parameter from ac_build_buffer_load 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
 2022-04-23 01:45:17 +00:00
Marek Olšák
3777a5d715 radeonsi: assign param export indices before compilation 
This moves the logic out of LLVM-specific codepaths.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
 2022-04-22 22:21:11 +00:00
Marek Olšák
4e8b8555c6 radeonsi: move si_shader_info::stage into si_shader_selector 
This will help me see all places where we use "info", which will
be moved from si_shader_selector to shader variants.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
 2022-04-22 22:21:11 +00:00
Marek Olšák
8de5b11b29 radeonsi: move most "info" fields from si_shader_selector into si_shader_info 
It's where they should be, and future commits might require this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
 2022-04-22 22:21:11 +00:00
Marek Olšák
a7b906264a radeonsi: add pipe_stream_output_info into si_shader_context 
to reduce deltas for the next commit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
 2022-04-22 22:21:11 +00:00
Yonggang Luo
2ca6ef22f7 util: Rename pipe_debug_callback to util_debug_callback 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15657>
 2022-04-01 01:52:43 +00:00
Yonggang Luo
523675e995 util: Rename pipe_debug_message to util_debug_message 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15657>
 2022-04-01 01:52:43 +00:00
Samuel Pitoiset
4cfb5332d6 radv: lower adjusting gl_FragCoord.z for VRS in NIR 
fossils-db (Sienna Cichlid):
Totals from 4432 (3.29% of 134913) affected shaders:
VGPRs: 231232 -> 231880 (+0.28%)
CodeSize: 24738224 -> 24718008 (-0.08%); split: -0.08%, +0.00%
MaxWaves: 93120 -> 93000 (-0.13%)
Instrs: 4540970 -> 4541062 (+0.00%); split: -0.01%, +0.01%
Latency: 49658353 -> 49641444 (-0.03%); split: -0.05%, +0.01%
InvThroughput: 9604328 -> 9603041 (-0.01%); split: -0.02%, +0.01%
VClause: 66497 -> 66498 (+0.00%)
SClause: 209530 -> 209532 (+0.00%); split: -0.01%, +0.01%
Copies: 276135 -> 276249 (+0.04%); split: -0.14%, +0.18%
PreSGPRs: 189409 -> 189415 (+0.00%)
PreVGPRs: 207368 -> 207458 (+0.04%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15450>
 2022-03-28 16:17:37 +02:00
Rhys Perry
15640e58d9 radv,aco: lower texture descriptor loads in NIR 
fossil-db (Sienna Cichlid):
Totals from 39445 (24.30% of 162293) affected shaders:
MaxWaves: 875988 -> 875972 (-0.00%)
Instrs: 35372561 -> 35234909 (-0.39%); split: -0.41%, +0.03%
CodeSize: 190237480 -> 189379240 (-0.45%); split: -0.47%, +0.02%
VGPRs: 1889856 -> 1889928 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 10764 -> 10857 (+0.86%); split: -2.04%, +2.91%
SpillVGPRs: 1891 -> 1907 (+0.85%); split: -0.32%, +1.16%
Scratch: 260096 -> 261120 (+0.39%)
Latency: 477701150 -> 477578466 (-0.03%); split: -0.06%, +0.03%
InvThroughput: 87819847 -> 87830346 (+0.01%); split: -0.03%, +0.04%
VClause: 673353 -> 673829 (+0.07%); split: -0.04%, +0.11%
SClause: 1385396 -> 1366478 (-1.37%); split: -1.65%, +0.29%
Copies: 2327965 -> 2229134 (-4.25%); split: -4.58%, +0.34%
Branches: 906707 -> 906434 (-0.03%); split: -0.13%, +0.10%
PreSGPRs: 1874153 -> 1862698 (-0.61%); split: -1.34%, +0.73%
PreVGPRs: 1691382 -> 1691383 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12773>
 2022-03-22 16:33:27 +00:00
Rhys Perry
c4cf92cad7 radv,aco,ac/llvm: fix indirect dispatches on the compute queue on GFX7-10 
Since neither PKT3_LOAD_SH_REG_INDEX nor PKT3_COPY_DATA work with compute
queues on GFX7-10, we have to load the dispatch size from memory in the
shader.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15064>
 2022-03-14 19:54:36 +00:00
Pierre-Eric Pelloux-Prayer
9685b5785b radeonsi: add SI_PROFILE_CLAMP_DIV_BY_ZERO 
To enable divide by zero clamping per shader, instead of per app.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14931>
 2022-02-16 11:13:25 +00:00
Marek Olšák
afdfcdd542 radeonsi: determine MEM_ORDERED after generating a shader variant 
because si_get_nir_shader runs NIR passes and some of them can introduce
new loads.

Fixes: 3fb77ef2e0 - radeonsi: do opt_large_constants & lower_indirect_derefs after uniform inlining

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14528>
 2022-01-18 11:11:08 +00:00
Marek Olšák
116a05c721 ac: move ac_exp_param.h to ac_nir.h 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
 2022-01-05 12:46:31 +00:00
Marek Olšák
2c4926dfc8 radeonsi: use nir->scratch_size instead of ac_count_scratch_private_memory 
It's the same.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
 2022-01-05 12:46:31 +00:00
Marek Olšák
12b942bd16 radeonsi: pass sample_coverage VGPR index to the PS prolog instead of guessing 
The code was correct, but little confusing. This is cleaner.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
 2022-01-05 12:46:30 +00:00
Samuel Pitoiset
8a327722d5 ac/nir: add an option to disable anisotropic filtering for single level images 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14171>
 2021-12-16 07:20:50 +00:00
Marek Olšák
d08b09cb7e radeonsi: use si_shader::wave_size 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
 2021-11-26 11:35:05 +00:00
Marek Olšák
9d7ac70ffb radeonsi: implement shader culling in GS 
It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák
492a61fe72 radeonsi: don't use ctx.stage outside of si_llvm_translate_nir 
si_llvm_translate_nir() changes ctx.stage, so the outside code shouldn't
use it. This hasn't caused any issues yet. Since ctx.stage starts as 0,
the first use in this commit was a tautology.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák
a368385b23 radeonsi: add is_gs parameter into si_vs_needs_prolog 
and disable the VS prolog code for GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák
8cf802e8ef radeonsi: replace the GS prolog with a monolithic shader variant 
It only exists because of the hw bug and is used very rarely.
Let's simplify it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13393>
 2021-10-18 18:08:59 +00:00
Marek Olšák
62798d2c1f radeonsi: don't pass NULL into si_get_nir_shader 
so that we always have the shader key there

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13393>
 2021-10-18 18:08:59 +00:00
Marek Olšák
8c5a32b5fe radeonsi: split si_shader_key into ps and ge parts to minimize memcmp overhead 
ps is for the pixel shader, while ge is for VS, TCS, TES, and GS.

si_shader_key: 68 bytes
si_shader_key_ge: 68 bytes
si_shader_key_ps: 28 bytes

The only notable change is that si_shader_select_with_key is changed
to a C++ template. Other changes are trivial.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13285>
 2021-10-16 10:41:51 +00:00
Marek Olšák
7b4427b199 radeonsi: enable NGG passthrough when LDS is used, document the real constraints 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
 2021-09-14 15:24:11 +00:00
Marek Olšák
5824ab569e radeonsi: precompute more spi_map code 
This replaces vs_output_param_offset by vs_output_ps_input_cntl,
which is easier to use.

For geometry shaders, vs_output_ps_input_cntl is stored in the GS si_shader
structure, not gs_copy_shader. This requires that gs_copy_shader compilation
is finished before the GS main shader part, so that GS can initialize
vs_output_ps_input_cntl using the compiled GS copy shader.

output_semantic_to_slot becomes unused, so it's removed.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
 2021-09-14 15:24:11 +00:00
Marek Olšák
576f8394db radeonsi: remove the primitive discard compute shader 
It doesn't always work, it's only useful on gfx9 and older, and it's too
complicated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4011

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
 2021-09-10 23:32:03 +00:00
Marek Olšák
3fb229e010 ac,radeonsi: load VS inputs at the call site of nir_intrinsic_load_input 
to match ACO

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12570>
 2021-09-07 17:51:41 +00:00
Marek Olšák
1e178f7a37 ac: make ac_shader_abi::inputs an array instead of a pointer 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12570>
 2021-09-07 17:51:41 +00:00
Marek Olšák
b141e50282 radeonsi: add optimal multi draws and draw-level splitting for prim discard CS 
This is a partial rewrite of some parts of the code.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11510>
 2021-06-28 13:23:14 +00:00
Marek Olšák
1e9cc86511 radeonsi: merge 2 conditional blocks with same condition into 1 in culling code 
The block only loads input VGPRs from LDS, and the next block uses them.
The entering condition is the same, even though the second block is
the next shader part beginning with the prolog.

Simply move the VGPR loads into the prolog.

This decreases the shader code size by 12 bytes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11102>
 2021-06-21 19:03:29 +00:00
Caio Marcelo de Oliveira Filho
8af6766062 nir: Move workgroup_size and workgroup_variable_size into common shader_info 
Move it out the "cs" sub-struct, since these will be used for other
shader stages in the future.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
 2021-06-08 09:23:55 -07:00
Caio Marcelo de Oliveira Filho
430d2206da compiler: Rename local_size to workgroup_size 
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
 2021-06-07 22:34:42 +00:00
Marek Olšák
64b75cc12e radeonsi: add a gfx10 hw bug workaround with the barrier before gs_alloc_req 
Fixes: 8845a23698 - amd: add NAVI10 PCI IDs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák
94a1f45e15 ac/llvm: set target features per function instead of per target machine 
This is a cleanup that allows the removal of the wave32 target machine and
the wave32 pass manager.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Samuel Pitoiset
936b58378c amd: drop support for LLVM 8 
It doesn't support Navi1x and the removal enables this nice code cleanup.

v2: rebase - mareko

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
 2021-04-16 09:25:19 +00:00
Marek Olšák
7db43960f6 radeonsi: implement 16-bit VS->PS varyings 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
 2021-04-13 21:10:43 -04:00
Bas Nieuwenhuizen
580f1ac473 nir: Extract shader_info->cs.shared_size out of union. 
It is valid for all stages, just 0 for most of them. In particular
mesh/task shaders might be using it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10094>
 2021-04-08 14:39:28 +00:00