Commit Graph

199956 Commits

Author SHA1 Message Date
Kenneth Graunke
93e186e1a4 brw: Delete pull constant lowering
Now that we never shrink ranges in the backend, we never lower push
constants to pull constants late in the backend either.  get_pull_loc
will never return true, and so all of brw_lower_constant_loads becomes
a noop.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Kenneth Graunke
1ab4fe2dd6 brw: Don't shrink UBO push ranges in the backend
Back in the bad old days (vec4?) we had a bunch of smarts in the backend
to dead code eliminate unused vector components and re-pack regular
uniforms, so we really couldn't decide how much data we were pushing
until very late in the backend.  Nowadays we have none of that - we do
all of our elimination and packing in NIR.  anv shrinks ranges to deal
with Vulkan API push constants, and iris treats everything as a UBO and
as of the previous commit will also shrink appropriately.

So we don't need to do this anymore...which will let us simplify quite
a bit of code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Kenneth Graunke
583ad35455 brw: Limit maximum push UBO ranges to 64 registers in the NIR pass.
anv already does this limiting, since it needs to handle non-UBO push
constants as well.  iris treats everything as a UBO, but doesn't have
a limiter and was relying on the backend to handle it.

Do this in the NIR pass so that we can eliminate the backend code.
It's not necessary for anv, but handling it here is simple and less
error prone for iris, which calls this in a number of places.  We know
we need to limit things to this much; anv can limit more if needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Feng Jiang
96c8eb64f0 virgl: Ensure that PIPE_SHADER_CAP_MAX_CONST_BUFFERS is less than PIPE_MAX_CONSTANT_BUFFERS
The value of the PIPE_SHADER_CAP_MAX_CONST_BUFFERS parameter should be
less than PIPE_MAX_CONSTANT_BUFFERS, otherwise, it will lead to some
assert failures. For example:

    void
    cso_unbind_context(struct cso_context *cso)
    {
    ...
        int maxsam = scr->get_shader_param(scr, sh,
                                           PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS);
        int maxview = scr->get_shader_param(scr, sh,
                                            PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS);
        int maxssbo = scr->get_shader_param(scr, sh,
                                            PIPE_SHADER_CAP_MAX_SHADER_BUFFERS);
        int maxcb = scr->get_shader_param(scr, sh,
                                          PIPE_SHADER_CAP_MAX_CONST_BUFFERS);
        int maximg = scr->get_shader_param(scr, sh,
                                          PIPE_SHADER_CAP_MAX_SHADER_IMAGES);
        assert(maxsam <= PIPE_MAX_SAMPLERS);
        assert(maxview <= PIPE_MAX_SHADER_SAMPLER_VIEWS);
        assert(maxssbo <= PIPE_MAX_SHADER_BUFFERS);
        assert(maxcb <= PIPE_MAX_CONSTANT_BUFFERS); // Crash here
        assert(maximg <= PIPE_MAX_SHADER_IMAGES);
    ...
    }

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32889>
2025-01-06 12:18:20 +00:00
Martin Roukala (né Peres)
f1a6af133a radeonsi/ci: run a fraction of glcts-vangogh in pre-merge
Now that ACO has become the default on pre-RDNA GPUs, all pre-merge CI
coverage of radeonsi+LLVM has disapeared. Let's fix this by making
our post-merge glcts-vangogh-valve job run inpre-merge pipelines.

However, we are limited in vangogh capacity, so rather than running the
full glcts/piglit test suites we run a fraction of it to stay under 15
minutes of execution time on a single Steam Deck.

Suggested-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32865>
2025-01-06 11:55:22 +00:00
Martin Roukala (né Peres)
0c538f82bc radeonsi/ci: run on ACO changes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32865>
2025-01-06 11:55:22 +00:00
Martin Roukala (né Peres)
bec7f09e76 radeonsi/ci: update the vangogh expectations
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32865>
2025-01-06 11:55:21 +00:00
Tapani Pälli
b1b1a4ef91 iris: initialize whole pipe_box struct for memcmp
Z and depth fields were given to memcmp uninitialized.

CID: 1637431
Fixes: 1fc82ee558 ("iris: Add support for damage region")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32857>
2025-01-06 09:18:52 +00:00
Tapani Pälli
72351afe24 anv: handle mesh in sbe_primitive_id_override
This prevents crashes seen in some upcoming cts tests.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32861>
2025-01-06 08:41:18 +00:00
David Rosca
36bedf6c80 frontends/va: Get buffer feedback with locked mutex in MapBuffer
Fixes: 93d434362b ("frontends/va: Move encode fence to coded buffer")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12344

Tested-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32761>
2025-01-06 08:19:08 +00:00
Hyunjun Ko
5ecea6ec4a anv: handle negative value of slot index for h265 decoding.
Fixes: 8d519eb5 ("anv: add initial video decode support for h265")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:14 +00:00
Hyunjun Ko
168298b891 anv: Enable remapping picture ID
Fix to handle 16 refs.

v1. handle the case where a slot index is negative.
(Lionel Landwerlin <lionel.g.landwerlin@intel.com>)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:14 +00:00
Hyunjun Ko
9221feaf79 anv: define ANV_VIDEO_H264_MAX_DPB_SLOTS
prep work for remapping slot ids for h264 decoding.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:13 +00:00
Erik Faye-Lund
61593e9c54 pan/ci: update opencl expectations
It's not entirely clear to me why this has moved from Crash/Fail to
Pass, the only thing I can see in the commit history between the last
nightly pass and failure is an optimization of unpacing 8-bit values
from a 64-bit value. It's a bit suspicious that an optimization makes
somethign pass...

But we need to have correct CI expectations, otherwise we won't notice
new failures. So let's update to the new reality, and debug this if the
problem reappears in the future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32833>
2025-01-05 07:44:04 +00:00
Erik Faye-Lund
f313b33d13 pan/ci: update t760 checksum
Looks like this changed when IO-lowering was changed in the GLSL
linker, but because the traces job here runs post-merge, it wasn't
noticed at the time.

There's only a single pixel that has changed, from a very dark color to
another very dark color. Neigher the before nor after images looks
obviously more correct than the other.

Fixes: 73d675451b ("ci: update fail lists and trace checksums")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32833>
2025-01-05 07:44:04 +00:00
David Rosca
e33452a6d3 ac/surface: Don't force linear for VIDEO_REFERENCE with emulated image opcodes
This caused regression by using higher pitch than needed on compute-only
devices, resulting in video decode errors.

Fixes: 308bae950f ("ac/surface: Add RADEON_SURF_VIDEO_REFERENCE")
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32863>
2025-01-04 09:13:44 +00:00
Rob Clark
fb59a9fb08 freedreno/a6xx: Use LATE_Z with OC + discard
If occlusion query is used, and the FS discards samples, we need to use
LATE_Z in order to get the sample count after the FS.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32869>
2025-01-04 02:52:41 +00:00
Lionel Landwerlin
98cdb9349a anv: ensure null-rt bit in compiler isn't used when there is ds attachment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15987f49bb ("anv: avoid setting up a null RT unless needed")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12396
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32867>
2025-01-03 23:12:22 +00:00
Caio Oliveira
6968794c50 intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+
Fix invalid SWSB annotation in dEQP-VK.glsl.builtin.precision.mix.mediump.vec4 for LNL.

Fixes: 4a24f49b57 ("intel/compiler/xe2: Implement codegen of three-source instructions.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32846>
2025-01-03 21:19:26 +00:00
Benjamin Lee
51b0bad30b panfrost/va: implement fquantizetf16 ftz
Bifrost implements this with a ftz flag in the clause header. Valhall
doesn't have clauses, and needs a separate flush instruction.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32470>
2025-01-03 20:53:36 +00:00
Benjamin Lee
c9de3d57f7 panfrost/va: add FLUSH instruction
This is needed to implement FTZ for intermediate values on valhall.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32470>
2025-01-03 20:53:36 +00:00
Benjamin Lee
9f17138571 panvk: remove load_multisampled_pan sysval
This was only used by bi_lower_sample_mask_writes, which now ignores it
in panvk due to panfrost_compile_inputs::single_sample_full_coverage.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32636>
2025-01-03 20:01:54 +00:00
Benjamin Lee
41c6148c0d panvk: handle sample mask writes on 1-sample targets
In OpenGL, non-multisample targets always have full coverage, and shader
writes to gl_SampleMask are ignored. On Vulkan, sample mask writes on
single-sample targets are treated the same way as writes with >1 sample.

Fixes dEQP-VK.pipeline.*.multisample_shader_builtin.write_sample_mask.1_samples

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32636>
2025-01-03 20:01:54 +00:00
Karol Herbst
5f30bc62fe rusticl/mesa/resource: port to NonNull
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
0fe59874c0 rusticl/mem: pass around QueueContext instead of PipeContext
This let us get rid of the Queue argument in a couple of places.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
b2f42dbe61 rusticl/queue: make QueueContext::dev public
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
d460cb3675 rusticl/mesa: add missing files to meson.build
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
f3f84cfe9f rusticl/mesa/context: use Default for pipe_grid_info initialization
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
a4cae3c6ed rusticl/device: remove unused functions
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
05b37f3968 rusticl/mem: remove mem_type argument from new_image
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
4cbd4bead7 rusticl/mesa: remove PipeTransfer::res
The pipe_transfer struct already stores a pointer to the pipe_resource, so
no need to store it inside the Rust wrapper as well.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
f667845741 include: Update the OpenCL headers to latest
A few breaking changes in rusticl which this also fixes.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
f75ba4f9e3 rusticl: stop using system headers for CL and GL
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Karol Herbst
ccfeda77bd rusticl/queue: add a life check to prevent applications dead locking
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32821>
2025-01-03 18:26:19 +00:00
Dylan Baker
f70ef03100 docs: update calendar for 24.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32870>
2025-01-03 10:00:51 -08:00
Dylan Baker
d518c59b9d docs: Add SHA sums to 24.3.3 release notes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32870>
2025-01-03 10:00:48 -08:00
Dylan Baker
0861975f49 docs: add release notes for 24.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32870>
2025-01-03 10:00:47 -08:00
Vinson Lee
3514b65c35 hk: Fix hk_ia_update arguments order
Fix defect reported by Coverity Scan.

Arguments in wrong order (SWAPPED_ARGUMENTS)
swapped_arguments: The positions of arguments in the call to
hk_ia_update do not match the ordering of the parameters:stat_c_inv is
passed to c_prims.stat_c_prims is passed to c_inv.

Fixes: a3b796ba19 ("libagx,hk: handle pipeline stats queries without a GS")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32853>
2025-01-03 17:14:48 +00:00
Erik Faye-Lund
eac8f1d460 Revert "panfrost: Disable CRC by default"
There's been a bunch of CRC fixes applied recently. Let's see if this
allows us to default to this as enabled instead.

This reverts commit fc30fe5bc5.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31965>
2025-01-03 12:12:15 +00:00
Lionel Landwerlin
1448778385 anv: rework tbimr push constant workaround
We'll want to know about the empty push constant for device generated
commands. It's easier if the information is stored in
anv_pipeline_bind_map::push_ranges[].

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32828>
2025-01-03 11:48:42 +00:00
Lionel Landwerlin
6281b207db anv: add tracepoints timestamp mode for empty dispatches
When the runtime is going to potentially emit no dispatch, we need to
have a way to capture a timestamp. Add a new flag for this to tell
whether we don't have a HW instruction to capture the timestamp and
rely on MI_STORE_REGISTER_MEM instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: de00fe3f66 ("anv: add BVH building tracking through u_trace")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12382
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32835>
2025-01-03 10:36:49 +00:00
Lionel Landwerlin
a224105a26 vulkan/runtime: avoid emitting empty build_leaves
Seen in GravityMark.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32835>
2025-01-03 10:36:49 +00:00
Zoltán Böszörményi
2b9b34887e docs/features: Mark more Vulkan 1.4 features as done for drivers
For nvk: VK_KHR_global_priority

For lvp: VK_KHR_global_priority, VK_KHR_index_type_uint8,
VK_KHR_line_rasterization, VK_KHR_load_store_op_none,
VK_KHR_shader_float_controls2, VK_KHR_shader_subgroup_rotate,
VK_KHR_vertex_attribute_divisor, VK_EXT_host_image_copy and
VK_EXT_pipeline_robustness.

Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32801>
2025-01-03 10:20:27 +00:00
Zoltán Böszörményi
43eaba013e docs/features: Mark VK_EXT_host_image_copy as implemented on Turnip
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32801>
2025-01-03 10:20:27 +00:00
Zoltán Böszörményi
a0931e3361 features.txt: Add Vulkan 1.4 section
Some extensions were moved to core.
See https://docs.vulkan.org/spec/latest/appendices/versions.html

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12392
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32801>
2025-01-03 10:20:27 +00:00
Valentine Burley
5fd9f08c1d lavapipe/ci: Re-enable lavapipe-vk-asan
The previous issues have been resolved, and the only error the
job encountered was due to incorrect expectations.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32832>
2025-01-03 10:02:05 +00:00
Samuel Pitoiset
03b037a0e3 radv: disable logic op for float/srgb formats
The Vulkan spec says:
    "The application can enable a logical operation between the
     fragment’s color values and the existing value in the framebuffer
     attachment. This logical operation is applied prior to updating
     the framebuffer attachment. Logical operations are applied only
     for signed and unsigned integer and normalized integer
     framebuffers. Logical operations are not applied to floating-point
     or sRGB format color attachments."

Missing VKCTS coverage has been reported.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12345
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32826>
2025-01-03 09:35:45 +00:00
Samuel Pitoiset
0019900312 radv/meta: do not create redundant pipeline layout objects
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32834>
2025-01-03 09:11:59 +00:00
Samuel Pitoiset
105e809a9d radv/meta: add radv_meta_get_noop_pipeline_layout()
To avoid duplicated objects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32834>
2025-01-03 09:11:59 +00:00
Samuel Pitoiset
dd7343f278 radv/meta: reduce length of some cache keys
For faster hashing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32834>
2025-01-03 09:11:59 +00:00