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Author SHA1 Message Date
Brian Paul
25a42f39e3 softpipe: add 'start' parameter to bind_sampler_states/views() 
To support updating a sub-range of sampler states/views in the future.
Note that we always pass start=0 at this time.
 2012-08-16 09:01:31 -06:00
Brian Paul
348ac08bfd gallium/trace: consolidate sampler, sampler_view code 2012-08-16 09:01:31 -06:00
Brian Paul
0ad95b923a gallium/identity: consolidate sampler, sampler_view code 
This will simplify things when the pipe_context functions are consolidated.
 2012-08-16 09:01:31 -06:00
Brian Paul
f3c3aff6ef st/mesa: add support for GS textures and samplers 2012-08-16 09:01:31 -06:00
Brian Paul
6c8a132158 st/mesa: combine vertex/fragment sampler state in arrays 
As with other recent changes, put the vertex and fragment sampler state
into arrays indexed by the shader type.  This will let us easily add
support for other types of shaders in the future.
 2012-08-16 09:01:31 -06:00
Brian Paul
cab2fed135 gallium: remove PIPE_MAX_VERTEX/GEOMETRY_SAMPLERS #define 
PIPE_MAX_SAMPLERS, PIPE_MAX_VERTEX_SAMPLERS and PIPE_MAX_GEOMETRY_SAMPLERS
were all defined to the same value (16).

In various places we're creating arrays such as
sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS] so we were assuming
the same number of max samplers for all shader stages anyway.

Of course, drivers are still free to advertise different numbers of max
samplers for different shaders.
 2012-08-16 09:01:31 -06:00
Brian Paul
a2c1df4c9a draw: index samplers and sampler_view state by shader type 
So that we can handle GS state and other types of shaders in the future.
 2012-08-16 09:01:31 -06:00
Brian Paul
bef196c792 draw: move tgsi-related state into a tgsi sub-struct 
To better organize things a bit.
 2012-08-16 09:01:31 -06:00
Brian Paul
df87fb5913 gallium: add a shader stage/type param to some draw functions 
To prepare for geometry shader texture support in the draw module.
Note: we still only handle the vertex shader case.
 2012-08-16 09:01:31 -06:00
Brian Paul
a8ed00d5f1 st/mesa: silence signed/unsigned comparison warning 2012-08-16 09:00:08 -06:00
Brian Paul
d733e5da9c svga: move result->key expression after result != NULL check 2012-08-16 08:58:55 -06:00
Brian Paul
50188adf7d svga: fix result==NULL logic in emit_fs_consts() 
The previous test for result != NULL was kind of bogus since we dereferenced
the pointer earlier in the code.  Now, check for result != NULL first, then
get the result->key info.

Also, remove the useless "offset +=" code at the end.
 2012-08-16 08:58:55 -06:00
Brian Paul
d55e0f1ba0 svga: update comment (s/SVGA_NEW_VS_RESULT/SVGA_NEW_VS_PRESCALE/) 2012-08-16 08:58:55 -06:00
Brian Paul
2a5eeeaebe svga: rename svga_hw_vs_parameters -> svga_hw_vs_constants 
and similarly for svga_hw_fs_parameters
 2012-08-16 08:58:55 -06:00
Niels Ole Salscheider
8cc1860d4a st/mesa: index can be negative in the PROGRAM_CONSTANT case 
NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-08-16 08:56:09 -06:00
Brian Paul
fd41cbc557 mesa: add cast to silence warning in _mesa_pack_rgba_span_from_ints() 2012-08-16 08:55:48 -06:00
Brian Paul
658044cde1 meta: remove unused variable 2012-08-16 08:53:55 -06:00
Michel Dänzer
1b11395a36 radeonsi: Fix symbol conflicts with r600g. 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50389

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 12:01:16 +02:00
Michel Dänzer
51d9f37a72 radeonsi: Fix memory leaks if returning early from some state functions. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
4b64fa2ff1 radeonsi: Fix LLVM context leak. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
18abc270c5 gallium/radeon: Don't assign virtual address space for BO that already has one. 
We'd end up re-using the old one and throwing away the new one anyway, but only
after a roundtrip to the kernel.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
a60be05284 gallium/radeon: Create hole for waste when allocating from va_offset. 
Otherwise, the wasted area could never be used for an allocation again.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
1f455ef5bc gallium/radeon: Fix potential address space loss in radeon_bomgr_force_va(). 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
6d59b7f6dc gallium/radeon: Delete uppermost virtual address space hole if it's at the top. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
f5fe81daea gallium/radeon: Fix losing holes when allocating virtual address space. 
If a hole exactly matches the allocated size plus alignment, we would fail to
preserve the alignment as a hole. This would result in never being able to use
the alignment area for an allocation again.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
206d07625c gallium/radeon: Merge holes when freeing virtual address space. 
Otherwise we'll likely end up with an ever increasing amount of ever smaller
holes.

Requires keeping the list ordered wrt offsets.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 09:39:36 +02:00
Michel Dänzer
c25968f3e2 gallium/radeon: Make va_offset 64 bits wide. 
Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU
virtual address space to 4GB anyway, but that will probably change sooner or
later, and this would result in confusing error messages when running out of
virtual address space even now.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 09:37:33 +02:00
Vinson Lee
1597176f70 llvmpipe: Silence Coverity incorrect sizeof expression defect. 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
 2012-08-15 22:15:49 -07:00
Vinson Lee
3d6892c479 scons: Add option to enable floating-point textures. 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
 2012-08-15 22:04:24 -07:00
Dave Airlie
6a3ac03f2b glx/dri2: add dri2 prime support. 
This adds support for having libGL pick a different driver for prime support.

DRI_PRIME env var is set to the value retrieved from the server randr
provider calls, by the calling process. (generally DRI_PRIME=1 will be
the right answer).

Signed-off-by: Dave Airlie <airlied@redhat.com>
 2012-08-16 10:02:10 +10:00
Vincent Lejeune
565a4e2a86 radeon/llvm: Enable if-cvt 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
a614979286 radeon/llvm: Add callbacks needed by if-cvt 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
0eca5fd919 radeon/llvm: Lower branch/branch_cond into predicated jump 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
6db2e9fdb0 radeon/llvm: Add a predicated JUMP instruction 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
8263408a91 radeon/llvm: Support for predicate bit 
Tom Stellard:
  - A few changes to predicate register defs

Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
8f597d57e9 r600g: Glue to handle predicate aware output from llvm 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
72f7632c6b r600g: Fix instruction group merge when there are predicated insts. 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
56227f875b radeon/llvm: Do not use PV/PS if PRED_SEL does not match 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
da676eab93 r600g: Add support for predicates 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Christian König
cf76edd300 radeonsi: move ps sampler state into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
ec5b698525 radeonsi: move ps sampler views into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
54de6f452c radeonsi: move vertex state descriptors into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
f2c95d93db radeonsi: add shader data infrastructure 
With this we can embed data for the shaders (like resource
descriptors) into the PM4 stream.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
4444b9d1ec radeon/llvm: add support to fetch temps as vectors 
Necessary for texture fetches with temp regs as source on SI.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Tom Stellard
b6051bc785 radeon/llvm: Remove AMDGPUUtil.cpp 2012-08-15 18:35:26 +00:00
Apostolos Bartziokas
040c2e0456 radeon/llvm: Cleanup AMDGPUUtil.cpp 2012-08-15 18:35:25 +00:00
Tom Stellard
3aaa209293 radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering 2012-08-15 18:35:25 +00:00
Tom Stellard
40c41fe890 radeon/llvm: Add live-in registers during DAG lowering 
Psuedo instructions emulating live-in registers have been removed
and their corresponding intrinsics are now being lowered during DAG
lowering.
 2012-08-15 18:35:25 +00:00
Tom Stellard
f3480f9234 radeon/llvm: Lower store_output intrinsic during DAG lowering 2012-08-15 18:35:25 +00:00
Tom Stellard
a76a0f7422 radeon/llvm: Force VTX_READ instructions to use same reg for src and dst 
I was seeing some GPU hangs that seemed to be cause by ALU instructions
writing to the same register used as the source for VTX_READ.  Adding
this constraint to the VTX_READ instructions avoids this situation.
 2012-08-15 18:35:25 +00:00