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20c5db02b570b946e6f029a0b5112df5376d010f
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72 Commits

Author SHA1 Message Date
Samuel Pitoiset
20c5db02b5 ac: add has_tc_compat_zrange_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:36 +02:00
Samuel Pitoiset
b55919cf2a ac: add has_gfx9_scissor_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:32 +02:00
Samuel Pitoiset
2b9c371575 ac: add cpdma_prefetch_writes_memory to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:29 +02:00
Samuel Pitoiset
b027ad66d7 ac: add has_out_of_order_rast to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:26 +02:00
Samuel Pitoiset
ed720af46d ac: add has_load_ctx_reg_pkt to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:22 +02:00
Samuel Pitoiset
63c0b89b8f ac: add has_rbplus to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:19 +02:00
Samuel Pitoiset
44a46c09de ac: add has_dcc_constant_encode to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:16 +02:00
Samuel Pitoiset
c08401f035 ac: add has_distributed_tess to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:11 +02:00
Samuel Pitoiset
d62d2840c4 ac: add has_clear_state to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:05 +02:00
Marek Olšák
19d04191c4 radeonsi: add support for compute-only chips 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-07-29 17:52:51 -04:00
Samuel Pitoiset
e510c5ee3b ac: import ac_get_compute_resource_limits() from RadeonSI 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-12 17:47:11 +02:00
Marek Olšák
3203a74dcb radeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDE 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Emil Velikov
4ec32413f3 ac: change ac_query_gpu_info() signature 
Currently libdrm_amdgpu provides a typedef of the various handles. While
the goal was to make those opaque, it effectively became part of the API

To the best of my knowledge there are two ways to have opaque handles:
 - "typedef void *foo;" - rather messy IMHO
 - "stuct foo;" and use "struct foo *" through the API

In our case amdgpu_device_handle is used only internally, plus
respective code is not used or applicable for r300 and r600. Hence we
copied the typedef.

Seemingly this will be a problem since libdrm_amdgpu wants to change the
API, while not updating the code(?).

Either way, we can safely s/amdgpU_device_handle/void */ and carry on.

Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
 2019-06-28 17:49:32 +01:00
Marek Olšák
0032f6b8a0 ac/surface: remove addrlib_family_rev_id 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-06-24 21:04:10 -04:00
Marek Olšák
abe9a51d27 ac: add radeon_info::is_amdgpu instead of checking drm_major == 3 
and clean up

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2019-06-14 13:31:18 -04:00
Marek Olšák
894e017c9c r600+radeonsi: use ctx_query_reset_status on radeon 
This allows a nice cleanup, because the winsys always handles it.
 2019-05-16 13:15:36 -04:00
Marek Olšák
b19884e08e winsys/amdgpu: add a parallel compute IB coupled with a gfx IB 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-05-16 13:07:00 -04:00
Marek Olšák
ccfcb9d818 ac: rename SI-CIK-VI to GFX6-GFX7-GFX8 
Acked-by: Dave Airlie <airlied@redhat.com>

We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.

It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.
 2019-05-15 20:54:10 -04:00
Marek Olšák
bfb9287599 ac: add radeon_info::is_pro_graphics 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-04-23 11:28:56 -04:00
Marek Olšák
64d6cc982d ac: add radeon_info::marketing_name, replacing the winsys callback 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-04-23 11:28:56 -04:00
Marek Olšák
1f21396431 radeonsi: add support for displayable DCC for multi-RB chips 
A compute shader is used to reorder DCC data from aligned to unaligned.
 2019-04-04 09:53:24 -04:00
Marek Olšák
2c09eb4122 radeonsi: add support for displayable DCC for 1 RB chips 
This is the simpler codepath - just disable RB and pipe alignment for DCC.
 2019-04-04 09:53:24 -04:00
Timothy Arceri
a53d68d318 ac/radv/radeonsi: add ac_get_num_physical_sgprs() helper 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2019-02-01 22:25:30 +11:00
Marek Olšák
fedc1fda30 radeonsi: save raster config in screen, add se_tile_repeat 2018-10-16 15:28:22 -04:00
Marek Olšák
bc09c3d59e ac: add radeon_info::num_good_cu_per_sh 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-09-10 15:19:56 -04:00
Marek Olšák
84652721b9 ac: add radeon_info::name 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-08-14 21:20:31 -04:00
Marek Olšák
a2451a4c23 ac/gpu_info: add radeon_info::num_tcc_blocks 
The values for the radeon winsys were copied from the kernel driver.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-06-19 12:52:28 -04:00
Marek Olšák
a2e9d9b4c1 ac/gpu_info: add has_read_registers_query 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:11 -04:00
Marek Olšák
9b1fdfc541 ac/gpu_info: add has_2d_tiling 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:10 -04:00
Marek Olšák
d26696283d ac/gpu_info: add has_sparse_vm_mappings 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:08 -04:00
Marek Olšák
125adc92ad ac/gpu_info: add has_unaligned_shader_loads 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:07 -04:00
Marek Olšák
e9c08bc658 ac/gpu_info: add has_indirect_compute_dispatch 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:03 -04:00
Marek Olšák
64265ac8d5 ac/gpu_info: add kernel_flushes_tc_l2_after_ib 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:01 -04:00
Marek Olšák
14c5a93bfa ac/gpu_info: add has_format_bc1_through_bc7 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:40:00 -04:00
Marek Olšák
2bd2c173e8 ac/gpu_info: add has_eqaa_surface_allocator 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:58 -04:00
Marek Olšák
e720cb6135 radeonsi: clean up the reset status query implementation 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:57 -04:00
Marek Olšák
3060f62340 ac/gpu_info: add has_bo_metadata 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:56 -04:00
Marek Olšák
09f1bab483 ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:54 -04:00
Marek Olšák
8b58a14ef7 ac/gpu_info: add htile_cmask_support_1d_tiling 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:53 -04:00
Marek Olšák
b81149e258 ac/gpu_info: add kernel_flushes_hdp_before_ib 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:47 -04:00
Dave Airlie
a90c9f33cf ac/radv/radeonsi: refactor harvest config register getters. 
This refactors the code out to share it between radv and radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2018-04-24 09:08:34 +10:00
Dave Airlie
f77caa7411 ac/radv/radeonsi: refactor max simd waves into common code. 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-04-24 09:08:33 +10:00
Dave Airlie
899df55ee0 ac/radv/radeonsi: refactor raster_config default values getters. 
This just makes this common code between the two drivers.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-04-24 09:07:51 +10:00
Dave Airlie
5e2ef28390 ac/info: move gs table depth to common code. 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-04-24 09:05:38 +10:00
Marek Olšák
5d91c2ccea ac/gpu_info: print GB_ADDR_CONFIG 2018-04-02 13:10:37 -04:00
Marek Olšák
b1f33086ec ac/gpu_info: reorder the fields and print them nicely 2018-04-02 13:10:37 -04:00
Marek Olšák
a0a96819e1 ac/gpu_info: rename has_virtual_memory -> r600_has_virtual_memory 2018-04-02 13:10:37 -04:00
Marek Olšák
769603564e radeonsi: don't reallocate on DMABUF export if local BOs are disabled 2018-03-26 19:22:12 -04:00
Marek Olšák
78ef16e2f9 winsys/amdgpu: query GDS info 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-08 14:58:16 -05:00
Marek Olšák
75c5d25f0f radeonsi: align command buffer starting address to fix some Raven hangs 
Cc: 17.3 18.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-08 14:58:16 -05:00