Commit Graph

193849 Commits

Author SHA1 Message Date
Eric Engestrom
1ba84bc5ca ci: add check for misleading indentation in ci toml files
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30442>
2024-08-22 20:25:32 +00:00
Lionel Landwerlin
d9406658ed brw: remove unused prog_data field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:40 +00:00
Lionel Landwerlin
cf986dd589 nir: remove unused intel intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:40 +00:00
Lionel Landwerlin
3769b58272 anv: move lowering of descriptor intrinsics to apply_layout
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:40 +00:00
Lionel Landwerlin
45117c0ed5 anv: simplify loading driver internal constants
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:39 +00:00
Lionel Landwerlin
7a55a930f6 anv: reuse common pipeline state for compute push allocations
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:39 +00:00
Denis
afb7b17fdd freedreno: Enable A505
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23630>
2024-08-22 19:11:52 +00:00
Robert Mader
70cdff1f23 perfetto: Add Panfrost data sources to system.cfg
Just like for msm and i915, so it works out-of-the-box.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28363>
2024-08-22 18:33:45 +00:00
Eric Engestrom
5a38361ba9 nvk/ci: document CTS bug
Thanks to @marysaka for identifying and reporting the bug:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/11736#note_2532965

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30793>
2024-08-22 18:20:55 +00:00
Connor Abbott
812c8f6abe tu: Treat partially-bound depth/stencil attachments as passthrough
Make sure to preserve the depth or stencil components of D24S8 using the
fixed codepath just added. While we're here, fix the detection of
whether an attachment is bound.

Fixes: cb0f414b ("tu: Add support for suspending and resuming renderpasses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26154>
2024-08-22 17:43:58 +00:00
Connor Abbott
5377219ca0 tu: Fix passthrough D24S8 attachments
We need to make sure that we don't trash a passthrough depth/stencil
aspect if we need to store the whole attachment by loading it
beforehand.

Fixes: cb0f414b ("tu: Add support for suspending and resuming renderpasses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26154>
2024-08-22 17:43:58 +00:00
Eric Engestrom
d7f7aede15 intel/ci: don't trigger anv-jsl-full & anv-tgl-full on GL changes
These are pure VK-CTS jobs, they don't run any GL tests.

It doesn't matter right now because these two jobs are disabled, but
when they get re-enabled, we'll want this to have been fixed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30677>
2024-08-22 16:24:24 +00:00
Daniel Stone
2a20cdfb31 ci/run_n_monitor: Add --dry-run argument
This will just print out the target jobs and their dependencies, then
exit.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:19 +00:00
Daniel Stone
ad5f4d0270 ci/run_n_monitor: Remove --force-manual
Now that we can exclude by stages instead, we don't need --force-manual.
Having mandatory arguments which also do the wrong thing is not great.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:19 +00:00
Daniel Stone
99cd56a684 ci/run_n_monitor: Add --exclude-stage filtering
Add an argument to ci_run_n_monitor specifying certain stages to be
excluded from consideration, defaulting to the one with post-merge and
performance jobs. This allows, e.g., to run all Panfrost pre-merge jobs:
./ci_run_n_monitor.py --target 'panfrost.*'

or to run all Freedreno pre-merge jobs:
./ci_run_n_monitor.py --target '.*' --include-stage freedreno

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:19 +00:00
Daniel Stone
3ffe733214 ci/run_n_monitor: Add --include-stage argument
Add basic filtering by stages, starting with stage inclusion.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
4e56472da2 ci/panfrost: Move manual/nightly jobs to postmerge stage
Create a new stage called arm-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
ca8f6b66a8 ci/etnaviv: Move manual/nightly jobs to postmerge stage
Create a new stage called etnaviv-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
b70ad23bb1 ci/nouveau: Move manual/nightly jobs to postmerge stage
Create a new stage called nouveau-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
337e00aa2d ci/llvmpipe: Move manual/nightly jobs to postmerge stage
Create a new stage called software-backends-postmerge and move the full
and manual jobs for both llvmpipe and lavapipe over there, to avoid
entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
4752ce7186 ci/zink: Move manual/nightly jobs to postmerge stage
Create a new stage called layered-backends-postmerge and move the full
and manual jobs over there, to avoid entanglement with the pre-merge
jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
25c70888a5 ci/broadcom: Move manual/nightly jobs to postmerge stage
Create new stages called broadcom-postmerge and freedreno-postmerge, and
move the full and manual jobs over there, to avoid entanglement with the
pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
cc507536db ci/intel: Move manual/nightly jobs to postmerge stage
Create a new stage called intel-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
4bcd57b0b5 ci/amd: Move manual/nightly jobs to postmerge stage
Create a new stage called amd-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Daniel Stone
f1aab081b5 ci: Create new 'performance' stage
Move all jobs doing performance testing to a separate stage.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
2024-08-22 15:35:18 +00:00
Job Noorman
97d049504c ir3: use physical cfg in helper_sched
We used the logical cfg in helper_sched under the assumption that (eq)
only kills active helpers. This could lead to something like this:

br p0.x, else
sam
(eq)nop
jump end
else:
sam
end:

It turns out this is not correct: (eq) kills *all* helpers so the
snippet above could produce wrong results.

To fix this, simply switch from using the logical cfg in helper_sched to
using the physical cfg.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
1bbc36c5d2 ir3: recalculate reconvergence after opt_jump
opt_jump destroys the physical cfg but it turns out we need it
afterwards in helper_sched. Keeping it correctly up-to-date during
opt_jump turned out to be tricky and complex. Simply recalculate it
afterwards to keep things simple.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
c67381538d ir3: fix reconvergence of blocks with multiple divergent predecessors
When calling ir3_calc_reconvergence after opt_jump, it may happen that
there are multiple divergent branches to the same block. This was
handled incorrectly since first_divergent_pred was unconditionally
overwritten for successors of divergent branches. This patch fixes this
by only making sure only the earliest divergent predecessor is used.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
d9977a6176 ir3: fix adding physical edges multiple times
After opt_jump, we might end up with weird control flow likes this:

block0: br block2
[more blocks]
block1: br block3
block2: ...
block3: ...

Since block2 is a logical successor of block1 (due to the fall through),
a physical edge will be added. However, another one will be added
because the branch to block3 crosses block2 (which is a reconvergence
point due to the branch from block0). This currently results in an
assert. This commit fixes this by ignoring successors of the start block
of edges that cross reconvergence points.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Connor Abbott
f432eb691e ir3: Move reconvergence backedge handling
Instead of handling backedges after a physical edge is added that extends
the divergence range, handle it at the beginning of the loop. This
handles the TODO by making sure that we also check for backedges after a
block is added to the worklist at the beginning due to a divergent
branch. For example, this fixes cases where opt_jump optimizes
"if (foo) { break; }" to remove the break block and we have a divergent
branch across the loop backedge.

While we're here, also fix an off-by-one that meant we wouldn't handle
backedges that jumped to the immediate previous block (which is again
possible after opt_jump) or the same block.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
aee097ed21 ir3: fix reconvergence points for blocks with two terminators
Blocks with two terminators have branches to both successors (instead of
a fall through to one) and hence need to mark both successors as
reconvergence points.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
fba921bf49 ir3: preserve block divergence info in ir3_lower_subgroups
We will need this to recalculate reconvergence after opt_jump.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:14 +00:00
Job Noorman
053612b7cf ir3: remove unnecessary reconvergence point in scan_clusters lowering
The body of the while loop does not need a reconvergence point since it
only has an incoming backwards branch.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:13 +00:00
Job Noorman
a13394ad91 ir3: print block divergence info
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:13 +00:00
Job Noorman
ec19a354dc ir3: print predicate inversion for branches
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29409>
2024-08-22 14:58:13 +00:00
Mike Blumenkrantz
13066905d3 egl/android: call dri2_display_create() like every other driver
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30773>
2024-08-22 14:22:41 +00:00
Rhys Perry
7b92e11e16 aco: forget valu delays after certain s_waitcnt_depctr/LDSDIR
fossil-db (navi31):
Totals from 55242 (69.58% of 79395) affected shaders:
Instrs: 40507666 -> 40138006 (-0.91%); split: -0.91%, +0.00%
CodeSize: 212516104 -> 211025880 (-0.70%); split: -0.70%, +0.00%
Latency: 281643258 -> 281628053 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 46370668 -> 46369637 (-0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23337>
2024-08-22 13:57:01 +00:00
Rhys Perry
30396ba604 aco: move insert_delay_alu to after insert_NOPs
s_delay_alu doesn't affect any hazards, but hazard workarounds don't
update s_delay_alu and so can make the s_delay_alu affect the wrong
instructions.

fossil-db (navi31):
Totals from 55777 (70.25% of 79395) affected shaders:
Instrs: 40740011 -> 40765017 (+0.06%)
CodeSize: 213768484 -> 213870856 (+0.05%); split: -0.00%, +0.05%
Latency: 283713083 -> 283714959 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 46551791 -> 46551835 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23337>
2024-08-22 13:57:01 +00:00
Rhys Perry
807651561e aco: split insert_wait_states into two
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23337>
2024-08-22 13:57:00 +00:00
Sergi Blanch Torne
ac9b13ace5 Revert "ci: disable Collabora's farm due to maintenance"
This reverts commit c5156257d9.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30777>
2024-08-22 13:06:03 +00:00
David Rosca
1ebff2220d frontends/va: Fix leaks with multiple coded buffer segments
The buffers can be reused, so we must only allocate added segments
and free unused segments.

Fixes: be4287c3aa ("pipe: Extend get_feedback with additional metadata")
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30779>
2024-08-22 12:20:22 +00:00
Connor Abbott
70934f3015 freedreno, tu, ir3: Enable tiled workgroup item dispatch on a7xx
There is a 1.6% improvement in the Sacha Willems computeshader demo.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30758>
2024-08-22 11:55:57 +00:00
Connor Abbott
58ed1854c4 freedreno/a7xx: Document compute dispatch tiling registers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30758>
2024-08-22 11:55:57 +00:00
Connor Abbott
c56683a3e2 freedreno/computerator: Fix enabling wave128
When adding API size controls we didn't update the assembler path. Make
it behave like it did before.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30758>
2024-08-22 11:55:57 +00:00
Erik Faye-Lund
9724d29b23 docs/panfrost: mention that Mali-G610 is conformant
We're conformant on Mali-G610 also these days, so let's mention that in
the docs as well!

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30783>
2024-08-22 11:47:47 +00:00
Samuel Pitoiset
d5efbc7f1c radv/amdgpu: fix CS padding for non-GFX/COMPUTE queues
I forgot that SDMA and VIDEO existed somehow.

Fixes: d690f293c6 ("radv/winsys: pad gfx and compute IBs with only one NOP")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30769>
2024-08-22 11:10:29 +00:00
Sergi Blanch Torne
c5156257d9 ci: disable Collabora's farm due to maintenance
Planned downtime in the farm:
* Start: 2024-08-22 06:00 UTC
* End: 2024-08-22 12:00 UTC

Risk notice due to electrical maintenance in the building where the farm
is hosted:
* Start: 2024-08-19 07:00 UTC
* End: 2024-08-22 16:00 UTC

So, there is a time window when the farm will be disabled. But there is
a bigger window when there is a change for this commit to be merged.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30534>
2024-08-22 07:18:22 +02:00
Mary Guillemard
e19871bd6a nak: Use F2FP for nir_op_pack_half_2x16_split on SM86+
On Ampere and later, this instruction allows to handle packing of F32x2
to F16x2.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30765>
2024-08-21 21:38:57 +00:00
Kenneth Graunke
6a292c2699 intel: Fix bad align_offset on global_constant_uniform_block_intel
We were specifying align_offset = 64 and align_mul = 64, which is
invalid.  nir_combined_align() asserts that align_offset < align_mul.

Our intention here is to perform cacheline-aligned (64B-aligned) block
loads, so we should set align_mul = 64 and can leave align_offset = 0.

Fixes: fbafa9cabd ("intel/nir: remove load_global_const_block_intel intrinsic")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30755>
2024-08-21 20:44:57 +00:00
Ian Romanick
c96ceb50d0 intel/brw/xe2: Allow int64 conversions
As far as I can tell from looking at the Bspec, MOV between integers
of all sizes appears to be supported.

shader-db:

total instructions in shared programs: 17480631 -> 17480535 (<.01%)
instructions in affected programs: 26284 -> 26188 (-0.37%)
helped: 21 / HURT: 13

total cycles in shared programs: 897601907 -> 897664293 (<.01%)
cycles in affected programs: 10929664 -> 10992050 (0.57%)
helped: 48 / HURT: 45

fossil-db:

Totals:
Instrs: 140686824 -> 140686155 (-0.00%); split: -0.00%, +0.00%
Cycle count: 21525129188 -> 21524717729 (-0.00%); split: -0.01%, +0.00%
Spill count: 70778 -> 70776 (-0.00%)
Fill count: 139172 -> 139168 (-0.00%)
Max live registers: 47513859 -> 47513795 (-0.00%)

Totals from 612 (0.11% of 549272) affected shaders:
Instrs: 964441 -> 963772 (-0.07%); split: -0.09%, +0.02%
Cycle count: 1215564312 -> 1215152853 (-0.03%); split: -0.09%, +0.06%
Spill count: 16172 -> 16170 (-0.01%)
Fill count: 37962 -> 37958 (-0.01%)
Max live registers: 70749 -> 70685 (-0.09%)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30700>
2024-08-21 20:16:00 +00:00