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Author SHA1 Message Date
Emma Anholt
191fa52d0c ci/turnip: Drop the IUB bug fallout flakes. 
They haven't been seen since my fix landed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
 2023-05-05 15:27:37 +00:00
Emma Anholt
12c10f2fe9 ci/turnip: Drop an xfail from the full run for a recent fix. 
Fixes: 2cbc24b9da ("turnip: fix buffer markers using wrong addresses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
 2023-05-05 15:27:37 +00:00
Emma Anholt
80b541513d ci/radv: Disable flaky heaven d3d9 trace. 
10 flakes this month, starting with the noted job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
 2023-05-05 15:27:37 +00:00
Emma Anholt
a8af504041 ci/radeonsi: Mark glx-make-current as flaky. 
It no longer 100% crashes, but instead sometimes fails.

Fixes: 91b06ea8b2 ("Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22863>
 2023-05-05 15:27:37 +00:00
Marcin Ślusarz
d6ece34418 intel/tools: decode ACTHD printed by newer kernels 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22874>
 2023-05-05 14:55:41 +00:00
Ruijing Dong
499f332a3a radeonsi/vcn: fix decoding bs buffer alignement issue. 
reason:
  in some cases, bs buffer size could cause assertion,
  and some bitstreams of certain resolutions could
  not be decoded.

solution:
  to align the bs buffer to 128.

fixes: 4f1646d73f

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22844>
 2023-05-05 14:20:21 +00:00
Mike Blumenkrantz
6d84b34359 zink: add ZINK_DEBUG=optimal_keys 
it's otherwise very annoying to figure out why this may or may not be
available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
 2023-05-05 12:32:40 +00:00
Mike Blumenkrantz
dcf3adbde7 zink: disable EXT_shader_object if !optimal_keys 
this has the same requirements as GPL and then some

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
 2023-05-05 12:32:40 +00:00
Mike Blumenkrantz
4cb900609f zink: break out optimal key handling into separate function 
this is growing to be much larger than the original conditional

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
 2023-05-05 12:32:40 +00:00
Mike Blumenkrantz
13f98c8101 zink: move EXT_shader_object check to another place 
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22854>
 2023-05-05 12:32:40 +00:00
Lionel Landwerlin
e64f5f261e anv: increase instruction heap to 2Gb 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8917
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin
c60e94d61f anv: make internal address space allocation more dynamic 
We're about to manipulate these pools and dealing with the fix address
ranges is painful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin
843afd4c63 anv: link anv_bo to its VMA heap 
We want to add more heaps in the future and so not having to do
address checks to find out in what heap to release a BO is convinient.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin
bb8e31b7ed anv: avoid hardcoding instruction VA constant in shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin
53b77a8102 anv: remove 48bit address space checks 
All the supported platforms should have 36+ bits of virtual address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Tapani Pälli
c35d430460 isl: fix layout for comparing surf and view properties 
These asserts were checking isl_format_layout against itself, change
to compare surface format layout against view format layout.

Fixes: 628bfaf1c6 ("intel/isl: Add some sanity checks for compressed surfaces")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22790>
 2023-05-05 08:48:53 +00:00
Lionel Landwerlin
9471ffa70a intel/fs: fix scheduling of HALT instructions 
With the following test :

dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load

There is a :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g1 = fbl
   g2 = broadcast g3, g1
   g4 = get_buffer_size g2
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

eliminate_find_live_channel will remove the fbl/broadcast because it
assumes lane0 is active at get_buffer_size :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g4 = get_buffer_size g0
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

But then the instruction scheduler will move the get_buffer_size after
the halt :

shader_start:
   ...                                 <- no control flow
   halt                                <- on some lanes
   g0 = some_alu
   g4 = get_buffer_size g0
   g5 = send <surface>, g4

get_buffer_size pulls the surface index from lane0 in g0 which could
have been turned off by the halt and we end up accessing an invalid
surface handle.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20765>
 2023-05-05 00:43:25 +03:00
Timur Kristóf
9b6945bb65 amd: Cleanup old GS intrinsics code. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:59 +00:00
Timur Kristóf
5bb04dc528 ac/nir/ngg: Use sendmsg in NGG lowering. 
There is no need to use alloc_vertices_and_primitives anymore,
because it will be compiled to sendmsg anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:59 +00:00
Timur Kristóf
025c1f5174 ac/nir: Emit legacy GS DONE signal in NIR. 
Legacy GS needs to emit a DONE signal at the end. Do this in NIR
instead of in the backends.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:59 +00:00
Timur Kristóf
fffb2b33af ac/nir: Use sendmsg in legacy GS lowering. 
Remove the GS intrinsics completely and emit the sendmsg here
instead of in the backend. This is done to simplify backend code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf
009f0623ff ac/llvm: Clarify arguments of ac_build_sendmsg. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf
28d740fc0b amd: Move sendmsg defines to ac_shader_util. 
Will be used by ac/nir legacy and NGG lowerings.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf
f66281c7fb amd: Add and implement gs_wave_id sysval. 
Contains a global wave ID of legacy GS waves.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf
c1591bfc28 amd: Add and implement sendmsg_amd intrinsic. 
This intrinsic is going to be used for simplifying GS code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Timur Kristóf
38447b3f63 aco: Disallow constant propagation on SOPP and fixed operands. 
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Rhys Perry
d5398b62da aco/ra: create M0-affinities for s_sendmsg 
v2 by Timur Kristóf:
Do not add the affinity for instructions that can't write m0
reliably, such as readlane-like instructions on GFX8.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
 2023-05-04 19:08:58 +00:00
Kenneth Graunke
9dd6fcd9ec intel/compiler: UNDEF SubgroupInvocation's register 
This value takes a few instructions to create, involving expanding
V-immediates, adding 8 for SIMD16, and so on.  We can mark it UNDEF
so that it's clear that although these are partial writes, we are
actually defining the entire value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
 2023-05-04 18:17:26 +00:00
Kenneth Graunke
4913f54a1f intel/compiler: UNDEF comparisons with smaller than 32-bit 
Comparisons which produce 32-bit boolean results (0 or 0xFFFFFFFF)
but operate on 16-bit types would first generate a CMP instruction
with W or HF types, before expanding it out.  This CMP is a partial
write, which leads us to think the register may contain some prior
contents still.  When placed in a loop, this causes its live range
to extend beyond its real life time.

Mark the register with UNDEF first so that we know that no prior
contents exist and need to be preserved.

This affects:
flt32, fge32, feq32, fneu32, ilt32, ult32, ige32, uge32, ieq32, ine32

On one of Cyberpunk 2077's most complex compute shaders, this reduces
the maximum live registers from 696 to 537 (22.8%).  Together with the
next patch, Cyberpunk's spills and fills are cut by 10.23% and 9.19%,
respectively.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
 2023-05-04 18:17:26 +00:00
Faith Ekstrand
fcdf28ad94 vulkan: Document vk_physical_device::supported_features 
While we're here, move it to after supported extensions to stay
consistent with the vk_physical_device_init parameters.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Constantine Shablya <constantine.shablya@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22845>
 2023-05-04 17:38:30 +00:00
antonino
96cd034e3c zink: take location_frac into account in pv emulation 
The pv mode emulation code was not taking into account the location_frac
of variables, they where beeing stored in a 1D array leading to
collisions.

Fixes: 5a4083349f ("zink: add provoking vertex mode lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22856>
 2023-05-04 16:28:44 +00:00
Illia Polishchuk
0843d4cbc3 nir: switch to a normal sampler for ARB program with not depth textures 
It is undefined behavior when an ARB assembly or shadow2d GLSL func
uses SHADOW2D target with a texture in not depth format.
In this case AMD and NVIDIA automatically replaces SHADOW sampler
with a normal sampler and some games like Penumbra Overture which abuses
this UB works fine but breaks with mesa.

Replace the shadow sampler with a normal one here by recompiling
the ARB program variant

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>
 2023-05-04 15:43:51 +00:00
Illia Polishchuk
f698d47571 drirc: add allow_sampled_tex_copy option 
From OpenGL spec 8.6
"An INVALID_OPERATION error is generated if the object bound to
READ_FRAMEBUFFER_BINDING is framebuffer complete and its effective
value of SAMPLE_BUFFERS (see section 9.2.3.1) is one"

But some games might do this

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>
 2023-05-04 15:43:51 +00:00
Collabora's Gfx CI Team
9e764eb8f8 Uprev Piglit to 79a084c56b6dd79f7c3a97b57a72963121ebb1e6 
355ad6bcb2...79a084c56b

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22548>
 2023-05-04 13:45:30 +00:00
Donald Robson
5edbf17e90 pvr: Move heap initialisation out of pvr_winsys_helper. 
This code will not be used by the new KMD, so it is being moved out of
this shared code area.

Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22826>
 2023-05-04 13:18:48 +00:00
David Heidelberg
2b4ce498ee panvk: clear dangling pointers 
Fixes:
```
[829/1646] Compiling C object src/panfrost/vulkan/libpanvk_v6.a.p/panvk_vX_meta_clear.c.o
In function 'panvk_meta_clear_zs_img',
    inlined from 'panvk_v6_CmdClearDepthStencilImage' at ../src/panfrost/vulkan/panvk_vX_meta_clear.c:457:7:
../src/panfrost/vulkan/panvk_vX_meta_clear.c:415:26: warning: storing the address of local variable 'view' in '((struct pan_fb_info *)((char *)commandBuffer + 144))[23].zs.view.zs' [-Wdangling-pointer=]
  415 |       fbinfo->zs.view.zs = &view;
      |       ~~~~~~~~~~~~~~~~~~~^~~~~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c: In function 'panvk_v6_CmdClearDepthStencilImage':
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'view' declared here
  393 |    struct pan_image_view view = {
      |                          ^~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'commandBuffer' declared here
[844/1646] Compiling C object src/panfrost/vulkan/libpanvk_v7.a.p/panvk_vX_meta_clear.c.o
In function 'panvk_meta_clear_zs_img',
    inlined from 'panvk_v7_CmdClearDepthStencilImage' at ../src/panfrost/vulkan/panvk_vX_meta_clear.c:457:7:
../src/panfrost/vulkan/panvk_vX_meta_clear.c:415:26: warning: storing the address of local variable 'view' in '((struct pan_fb_info *)((char *)commandBuffer + 144))[23].zs.view.zs' [-Wdangling-pointer=]
  415 |       fbinfo->zs.view.zs = &view;
      |       ~~~~~~~~~~~~~~~~~~~^~~~~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c: In function 'panvk_v7_CmdClearDepthStencilImage':
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'view' declared here
  393 |    struct pan_image_view view = {
      |                          ^~~~
../src/panfrost/vulkan/panvk_vX_meta_clear.c:393:26: note: 'commandBuffer' declared here
```

Cc: mesa-stable

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22829>
 2023-05-04 15:02:44 +02:00
Lionel Landwerlin
f3d648d20d anv: implement VK_KHR_ray_tracing_position_fetch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin
5cdcc22736 intel/nir/rt: wire position fetch intrinsic 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin
03f0f70adf intel/nir/rt: use a single load for instance leaf loading 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin
1e0e4657f9 spirv/nir: wire ray interection triangle position fetch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin
dcdf008d6f spirv: update to latest headers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin
3e726435cc vulkan: bump headers to 1.3.249 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Jarred Davies
eb233576d8 pvr: Reduce free list initial size when multiple devices are created 
Will hopefully reduce the memory load when running dEQP.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22330>
 2023-05-04 11:06:57 +00:00
Jarred Davies
6005d28249 pvr: Use vk_device's enabled features struct 
Avoids duplicating the struct in pvr_device and fixes uninitialized
accesses when ppEnabledFeatures was NULL.

Noticed when running valgrind over dEQP.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22331>
 2023-05-04 10:51:11 +00:00
Jarred Davies
0164425b38 pvr: Don't ralloc build context from compiler 
rogue_compiler is allocated for each VkPhysicalDevice which means it can
be used from multiple threads when compiling. Allocating the build context
from this will lead to race conditions as ralloc is not thread safe.

Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22332>
 2023-05-04 10:35:30 +00:00
nihui
2cc0b4a813 panvk: port panvk_logi to vk_logi 
Signed-off-by: Hui Ni <shuizhuyuanluo@126.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22772>
 2023-05-04 10:15:35 +00:00
James Glanville
ba118bb3bc pvr: Adjust clear's region clip words 
Co-Authored-By: : Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>
 2023-05-04 08:42:31 +00:00
James Glanville
beffefbf21 pvr: Fix incorrect PBE packmode for S8_UINT 
Fixes:
dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states
  .fail_keep.pass_keep.dfail_keep.comp_always

Signed-off-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>
 2023-05-04 08:42:31 +00:00
Karmjit Mahil
0aafa22a1c pvr: Don't advertise S8_UINT support 
S8_UINT is not a requirement for Vulkan 1.0.

Revert "pvr: Add initial support for VK_FORMAT_S8_UINT".

This reverts commit 220356e083.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>
 2023-05-04 08:42:31 +00:00
SoroushIMG
57d6cb2f1e pvr: fix sync waiting while using pvrsrvkm 
pvrsrvkm type sync objects can have a pending state where,
the fence is unsignaled but does not have a valid sync file
due to not yet being submitted to kernel.

The wait function therefore needs to handle these types of syncs
through a spin loop.

This was seen as crashes in dEQP-VK.synchronization.timeline_semaphore.*

Signed-off-by: SoroushIMG <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22822>
 2023-05-04 08:42:31 +00:00