Commit Graph

13 Commits

Author SHA1 Message Date
Brian Paul
1839a7fc9f intel: remove intel_span_supports_format()
It always returned True.
2012-01-24 14:12:34 -07:00
Brian Paul
14da67d9b9 intel: make intel_renderbuffer_map/unmap() static 2012-01-24 14:12:13 -07:00
Eric Anholt
92054cd94e intel: Add an implementation of MapRenderbuffer.
v2: Add separate stencil S8 W-tile swizzling/deswizzling.  Tested for
    the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1
    ./bin/hiz-depth-stencil-test-fbo-d24-s8
v3: Apply Chad's fix for S8 window system buffers.

Reviewed-by: Chad Versace <chad@chad-versace.us>
2011-11-01 15:42:17 -07:00
Eric Anholt
e339b669a1 intel: Add a couple of helper functions to reduce rb code duplication. 2010-12-10 15:37:16 -08:00
Kristian Høgsberg
f9995b3075 Drop GLcontext typedef and use struct gl_context instead 2010-10-13 09:43:25 -04:00
Eric Anholt
7d4b7460b0 i915: Enable ARB_vertex_shader for both i915 and i830.
Since the TNL is all done in software anyway, it should be the same to
the user who's probably using ARB_vertex_program otherwise, but gives them
a nicer programming environment.
2009-10-01 14:31:03 -07:00
Dave Airlie
f75843a517 Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c.
2008-08-24 17:59:10 +10:00
Dave Airlie
7c81124d7c Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-24 17:52:40 +10:00
Eric Anholt
bdaa06ad63 intel: move renderbuffer mapping to separate functions.
This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish.  Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
2008-07-23 10:21:24 -07:00
Eric Anholt
2e841880cf drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. 2008-07-11 18:58:19 -07:00
Eric Anholt
19f585a3cf intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode.  Instead, guess the correct
tiling in screen setup.

Also, fix the Y-tiling pitch setup.  The pitch to the next tile in Y is
32 scanlines, not 8.
2008-07-02 09:10:21 -07:00
Keith Packard
537bbe6dec [intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
2008-05-06 10:51:08 -07:00
Eric Anholt
77a5bcaff4 [intel] Move over files that will be shared with 965-fbo work. 2007-11-09 14:27:33 -08:00