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86 Commits

Author SHA1 Message Date
Marek Olšák
15d918e46f radeonsi: inline struct si_sampler_views 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-06 02:56:11 +02:00
Marek Olšák
06bfb2d28f r600: fork and import gallium/radeon 
This marks the end of code sharing between r600 and radeonsi.
It's getting difficult to work on radeonsi without breaking r600.

A lot of functions had to be renamed to prevent linker conflicts.
There are also minor cleanups.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-09-26 04:21:14 +02:00
Samuel Pitoiset
f0d09d9012 radeonsi: move si_get_wave_info() to AMD common code 
This will allow us to use it from radv.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2017-09-14 10:37:57 +02:00
Nicolai Hähnle
7e4344151f radeonsi: fix segfault in descriptor dumping 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-09-13 18:24:18 +02:00
Nicolai Hähnle
274f1dace7 amd/common: pass chip_class to ac_dump_reg 
Acked-by: Marek Olšák <marek.olsak@amd.com>
 2017-09-06 09:59:17 +02:00
Nicolai Hähnle
55df3d2286 radeonsi: fix compute shader state dumping 
Fixes: 420c438589 ("radeonsi: log draw and compute state into log context")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-09-04 13:50:47 +02:00
Samuel Pitoiset
12cbd9a13f radeonsi: move si_vm_fault_occured() to AMD common code 
For radv, in order to report VM faults when detected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2017-09-01 09:46:32 +02:00
Bas Nieuwenhuizen
46dd30d08f ac/debug: Support multiple trace ids for nested IBs. 
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
 2017-08-29 23:05:59 +02:00
Marek Olšák
113278ee79 radeonsi: remove Constant Engine support 
We have come to the conclusion that it doesn't improve performance.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-08-22 13:29:47 +02:00
Nicolai Hähnle
a6e7693882 gallium: remove unused PIPE_DUMP_* defines 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-08-22 09:53:35 +02:00
Nicolai Hähnle
420c438589 radeonsi: log draw and compute state into log context 
Also add missing trace emits and CS logging for compute launches.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-08-22 09:53:34 +02:00
Nicolai Hähnle
4c3f36ec6b radeonsi: print saved CS to the log context 
Use the auto logger facility, so that CS chunks will be interleaved
with other log info.

v2:
- fix some crashes when not using CE
- fix skipping "previous" chunks of current (unflushed) IB
- fix error handling in si_begin_cs_debug

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-08-22 09:53:14 +02:00
Nicolai Hähnle
bc93339799 radeonsi: start using u_log_context for debugging 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-08-22 09:51:00 +02:00
Nicolai Hähnle
ad33f2ddd8 radeonsi: re-order debug state dumping 
Keep together the parts that won't use the deferred logging mechanism.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-08-22 09:50:57 +02:00
Marek Olšák
1aeafb59e6 radeonsi: print CE IBs into ddebug reports 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-08-01 17:06:38 +02:00
Marek Olšák
1482861abe radeonsi: fix printing vertex buffer descriptors into ddebug reports 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-08-01 17:06:38 +02:00
Marek Olšák
c62809171c radeonsi/gfx9: add VM fault dmesg parser support 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-07-17 10:57:34 -04:00
Marek Olšák
aaee0d1bbf gallium: use "ull" number suffix to keep the QtCreator parser happy 
It can't parse "llu".

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
 2017-07-10 22:44:48 +02:00
Marek Olšák
3fc99f1299 radeonsi: fix dumping shader descriptors into ddebug logs 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-06-19 20:16:20 +02:00
Marek Olšák
5df24c3fa6 radeonsi: merge constant and shader buffers descriptor lists into one 
Constant buffers: slot[16], .. slot[31] (ascending)
Shader buffers: slot[15], .. slot[0] (descending)

The idea is that if we have 4 constant buffers and 2 shader buffers, we only
have to upload 6 slots. That optimization is left for a later commit.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-05-18 22:15:02 +02:00
Nicolai Hähnle
3811730a37 radeonsi: silence a Coverity warning 
Coverity doesn't understand that we'll never pass non-NULL for vertex
shaders.

This is a bit lame, actually. A straightforward cross-procedural analysis
limited to this source file should be enough to prove that there's no
NULL-pointer dereference. Oh well.

CID: 1405999
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-16 16:11:54 +02:00
Nicolai Hähnle
362f8f6798 radeonsi: dump compute descriptor lists 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-10 08:58:53 +02:00
Nicolai Hähnle
30267256df radeonsi: dump both enabled and required descriptor slots 
This allows a meaningful dump with info == NULL (for compute shaders).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-10 08:58:50 +02:00
Nicolai Hähnle
571597bf47 radeonsi: dump compute shader as part of debug dump 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-10 08:58:48 +02:00
Nicolai Hähnle
1a3bedd4b7 radeonsi: split descriptor list dumping 
Prepare for dumping CS descriptor list.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-10 08:58:44 +02:00
Nicolai Hähnle
83f56e531d radeonsi: split shader dumping 
Prepare for dumping compute shaders.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-05-10 08:58:41 +02:00
Marek Olšák
dcea7e5d19 radeonsi: add si_shader::prolog2 
For a GS prolog in merged ES-GS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
a98c9ba580 radeonsi/gfx9: add si_shader::previous_stage for merged shaders 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-04-28 21:47:35 +02:00
Marek Olšák
a0e8b73594 radeonsi/gfx9: update r600_print_texture_info 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
92112ec296 radeonsi/gfx9: don't read back non-existent SRBM registers 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
ef97cc0cae radeonsi/gfx9: add IB parser support 
Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.

The Python script parses both headers like one stream and tries to merge
all definitions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Timothy Arceri
dc4c551a34 radeon/ac: switch from radeon_elf_read() to ac_elf_read() 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-02-28 13:20:31 +11:00
Timothy Arceri
69a687189e radeon/ac: switch from radeon_shader_binary to ac_shader_binary 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-02-28 13:20:31 +11:00
Marek Olšák
28c06b3ceb radeonsi: write shader asm annotated with wave info into GPU hang reports 
Note that the disassembly is written twice - first the unmodified compiler
output and then the wave-annotated output only if there are waves executing
the shader.

Sample output from a real GPU hang most likely caused by image_sample:

The number of active waves = 28

Pixel Shader - annotated disassembly:
    s_mov_b64 s[6:7], exec                                        ; BE86017E [PC=0x10f3e3800, off=0, size=4]
    s_wqm_b64 exec, exec                                          ; BEFE077E [PC=0x10f3e3804, off=4, size=4]
...
    image_sample v[7:9], v[0:1], s[12:19], s[20:23] dmask:0x7     ; F0800700 00A30700 [PC=0x10f3e3a94, off=660, size=8]
    s_buffer_load_dword s20, s[0:3], 0x50                         ; C0220500 00000050 [PC=0x10f3e3a9c, off=668, size=8]
    s_load_dwordx4 s[24:27], s[4:5], 0x170                        ; C00A0602 00000170 [PC=0x10f3e3aa4, off=676, size=8]
    s_load_dwordx8 s[12:19], s[4:5], 0x140                        ; C00E0302 00000140 [PC=0x10f3e3aac, off=684, size=8]
    s_buffer_load_dword s11, s[0:3], 0x5c                         ; C02202C0 0000005C [PC=0x10f3e3ab4, off=692, size=8]
    s_buffer_load_dword s21, s[0:3], 0x54                         ; C0220540 00000054 [PC=0x10f3e3abc, off=700, size=8]
    s_buffer_load_dword s22, s[0:3], 0x58                         ; C0220580 00000058 [PC=0x10f3e3ac4, off=708, size=8]
    s_waitcnt vmcnt(0)                                            ; BF8C0F70 [PC=0x10f3e3acc, off=716, size=4]
          ^ SE0 SH0 CU1 SIMD1 WAVE0  EXEC=aaaaaaa555aaaaaa  INST32=BF8C0F70
          ^ SE0 SH0 CU1 SIMD2 WAVE0  EXEC=aaaa85555555552a  INST32=BF8C0F70
          ^ SE0 SH0 CU1 SIMD3 WAVE0  EXEC=000000000000000a  INST32=BF8C0F70
          ^ SE0 SH0 CU6 SIMD1 WAVE0  EXEC=25a5a5aa82aaaaaa  INST32=BF8C0F70
          ^ SE0 SH0 CU6 SIMD3 WAVE0  EXEC=50aaaa8fffa55555  INST32=BF8C0F70
          ^ SE0 SH0 CU7 SIMD0 WAVE0  EXEC=5554aaaaaaa1a555  INST32=BF8C0F70
          ^ SE0 SH0 CU7 SIMD0 WAVE1  EXEC=aaaa5555ffffffff  INST32=BF8C0F70
          ^ SE0 SH0 CU7 SIMD1 WAVE0  EXEC=555557aaaaaaaaa5  INST32=BF8C0F70
          ^ SE0 SH0 CU7 SIMD3 WAVE0  EXEC=5555aaaaaaaaaa85  INST32=BF8C0F70
          ^ SE1 SH0 CU3 SIMD1 WAVE0  EXEC=aaaaaaaaaaaaaaaa  INST32=BF8C0F70
          ^ SE1 SH0 CU4 SIMD0 WAVE0  EXEC=aaaaaaaa5a5a5a5a  INST32=BF8C0F70
          ^ SE1 SH0 CU4 SIMD1 WAVE0  EXEC=aaaaaaa5a5a5a4a5  INST32=BF8C0F70
          ^ SE1 SH0 CU4 SIMD2 WAVE0  EXEC=5555555000000000  INST32=BF8C0F70
          ^ SE1 SH0 CU4 SIMD3 WAVE0  EXEC=aa555554155aaaaa  INST32=BF8C0F70
          ^ SE1 SH0 CU5 SIMD0 WAVE0  EXEC=55ffff55555555aa  INST32=BF8C0F70
          ^ SE1 SH0 CU5 SIMD1 WAVE0  EXEC=555555555aaaaaaa  INST32=BF8C0F70
          ^ SE1 SH0 CU5 SIMD2 WAVE0  EXEC=a0aaaaaaa8555555  INST32=BF8C0F70
          ^ SE1 SH0 CU5 SIMD3 WAVE0  EXEC=8aaaaaaaaaaaa555  INST32=BF8C0F70
          ^ SE1 SH0 CU6 SIMD0 WAVE0  EXEC=000000002aaaaaaa  INST32=BF8C0F70
          ^ SE2 SH0 CU1 SIMD0 WAVE0  EXEC=5aaaa5400aaaa15a  INST32=BF8C0F70
          ^ SE2 SH0 CU1 SIMD1 WAVE0  EXEC=00aaaaaaaa5555aa  INST32=BF8C0F70
          ^ SE2 SH0 CU1 SIMD2 WAVE0  EXEC=aa00005555554555  INST32=BF8C0F70
          ^ SE2 SH0 CU1 SIMD3 WAVE0  EXEC=aaaaaaa000000000  INST32=BF8C0F70
          ^ SE3 SH0 CU4 SIMD0 WAVE0  EXEC=5555aaaaaaaaaaaa  INST32=BF8C0F70
          ^ SE3 SH0 CU4 SIMD2 WAVE0  EXEC=ffaaaaaaaaaa5555  INST32=BF8C0F70
          ^ SE3 SH0 CU4 SIMD3 WAVE0  EXEC=aaaa55555555aa00  INST32=BF8C0F70
          ^ SE3 SH0 CU5 SIMD0 WAVE0  EXEC=00aaaaaaaaaaaa5a  INST32=BF8C0F70
          ^ SE3 SH0 CU5 SIMD1 WAVE0  EXEC=5a555555005555ff  INST32=BF8C0F70
    v_mul_f32_e32 v7, s6, v7                                      ; 0A0E0E06 [PC=0x10f3e3ad0, off=720, size=4]
...

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-02-10 11:27:50 +01:00
Marek Olšák
3de8c5a3c5 radeonsi: write wave information into GPU hang reports 
UMR is our new debugging tool. It must have +s set for Mesa to use it
without root privileges:
  sudo chmod +s .../umr

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-02-10 11:27:50 +01:00
Bas Nieuwenhuizen
8cb60c7dd3 ac/debug: Dump indirect buffers. 
This is for handling chained command buffers and secondary command
buffers. It doesn't handle the trace id for secondary command buffers
yet, but I don't think that is possible in general with just writes,
as we could call a secondary command buffer multiple times.

I think this is good enough for now, as the most useful case is the
chaining when we grow an IB.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
 2017-01-09 21:44:08 +01:00
Bas Nieuwenhuizen
0ef1b4d5b1 ac/debug: Move IB decode to common code. 
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
 2017-01-09 21:43:59 +01:00
Marek Olšák
6f356d15be radeonsi: cleanly communicate whether si_shader_dump should check R600_DEBUG 
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-01-09 12:01:30 +01:00
Samuel Pitoiset
7d48a84b16 radeonsi: capitalize VM hex addr when dumping buffer list 
Useful when debugging with R600_DEBUG=vm,check_vm to match
addr in both outputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-01-04 10:14:22 +01:00
Marek Olšák
57b9d75af5 radeonsi: write shader descriptors into hang reports 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-12-07 19:40:29 +01:00
Marek Olšák
ea43d0b5e8 radeonsi: don't print bodies of header-only packets 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-11-29 23:52:31 +01:00
Marek Olšák
7abd94c9b0 radeonsi: print unknown registers with correct formatting 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-11-29 23:52:31 +01:00
Marek Olšák
8c6ea5a6ff radeonsi: remove unnecessary #includes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
 2016-10-04 16:12:07 +02:00
Marek Olšák
ca1d1e0e19 radeonsi: parse SURFACE_SYNC correctly on CIK-VI 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
 2016-10-04 16:11:49 +02:00
Marek Olšák
84860dd0bb radeonsi: print the IB and buffer list in VM fault reports 
This is a fallout from reworking the debug flags.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-09-13 20:38:25 +02:00
Marek Olšák
7172906c0c radeonsi: fix printing shaders and states on a VM fault 
This was missed while rewriting the PIPE_DUMP flags.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2016-08-26 15:50:10 +02:00
Marek Olšák
bcfd49e511 gallium/radeon: increase priority for shader binaries 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2016-08-26 15:50:10 +02:00
Marek Olšák
c3f716fe67 gallium/radeon: merge USER_SHADER and INTERNAL_SHADER priority flags 
there's no reason to separate these

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2016-08-26 15:50:10 +02:00
Marek Olšák
1ac23a9359 gallium/radeon: assign the highest priority to scratch; make rings second 
just FYI, the kernel receives priority/4

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-08-17 14:15:29 +02:00
Marek Olšák
95020c6dfd gallium/radeon: mark shader rings as highest-priority buffers 
and rename the enum

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-08-17 12:24:35 +02:00