Commit Graph

48947 Commits

Author SHA1 Message Date
Brian Paul
84c7c14697 st/mesa: pass GL_MAP_INVALIDATE_RANGE_BIT to gallium drivers
when mapping renderbuffers or texture images.

NOTE: This is a candidate for the 8.0 branch.
2012-01-18 10:44:05 -07:00
Brian Paul
64fdfefb9d mesa: use GL_MAP_INVALIDATE_RANGE_BIT in glTexImage paths
Update the dd.h docs to indicate that GL_MAP_INVALIDATE_RANGE_BIT
can be used with GL_MAP_WRITE_BIT when mapping renderbuffers and
texture images.

Pass the flag when mapping texture images for glTexImage, glTexSubImage,
etc.  It's up to drivers whether to actually make use of the flag.

NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-01-18 10:44:05 -07:00
Brian Paul
1d7048f12e mesa: try RGBA_FLOAT16 before RGBA_FLOAT32 when choosing A,L,LA,I formats
To try to use less tex memory and maybe get better performance.
Spotted by Roland Scheidegger.

NOTE: This is a candidate for the 8.0 and 7.11 branches.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-01-18 10:44:05 -07:00
Brian Paul
7628696004 mesa: fix tex format selection for GL_R32F and other R/G float formats
The i965 driver advertises GL_ARB_texture_float and GL_ARB_texture_rg
support but the ctx->TextureFormatSupported[] table entries for
MESA_FORMAT_R_FLOAT32 and MESA_FORMAT_RGBA_FLOAT32 are false on gen 4
hardware.  So the case for GL_R32F would fail and we'd print an
implementation error.

This patch adds more Mesa tex format options for GL_R32F and other R/G
formats so we fall back to 16-bit formats when 32-bit formats aren't
available.

Eric made the same fix in commit 6216a5b4 for the non R/G formats.

v2: try 16-bit formats before 32-bit formats and try RG formats before
RGBA where possible.

This should fix https://bugs.freedesktop.org/show_bug.cgi?id=44039

NOTE: This is a candidate for the 8.0 and 7.11 branches.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2012-01-18 10:44:05 -07:00
Brian Paul
481011ffcd docs: add more potential dependencies for vmware guest driver 2012-01-18 10:44:05 -07:00
Alexander von Gluck IV
5481b5adcf scons: Add more machine architectures to the machine map
* BePC, BeBox, BeMac for Haiku.
* Add sparc architecture as Mesa looks for it.

Signed-off-by: José Fonseca <jfonseca@vmware.com>
2012-01-18 16:46:16 +00:00
Dave Airlie
0196433ce5 r600g: fix ISLT on r600/700
This fixes ISLT like evergreen.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-18 22:14:49 +10:00
Dave Airlie
5893e686b6 r600g: make r600/700 use correct ineg.
Noticed by Vadim Girlin on irc.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-18 21:54:07 +10:00
Dave Airlie
1fc001ea15 r600g: fix some of the interpolation tests.
This enables linear gradients if we need a linear,
it also sets the flat shade flag for color/constant interpolations.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-18 20:13:16 +10:00
Kenneth Graunke
5acc7f38d4 i965: Bump Ivybridge's fake MRF range to g112-127 instead of g111-126.
When I originally implemented the hack to use GRFs 111+ as fake MRFs, I
did so purely to avoid rewriting all the code that dealt with MRFs.
However, it turns out that a similar hack is actually required.

Newly discovered language in the BSpec indicates that SEND instructions
with EOT set "should" use g112-g127 as their source registers.  Based on
assertions in the simulator, this is actually a requirement on certain
platforms.

Since we're faking MRFs already, we may as well use the officially
sanctioned range.  My guess is that we avoided this issue because we
seldom use m0: URB writes in the new VS backend start at m1, and RT
writes in the new FS backend start at m2.

NOTE: This is a candidate for stable release branches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-01-18 00:45:01 -08:00
Kenneth Graunke
bdedd03b70 i965: Remove the INTEL_OLD_VS option.
Now that we no longer generate Mesa IR from GLSL IR, it's impossible to
use the old vertex shader backend for GLSL programs.  There's simply no
Mesa IR to codegen from.

Any attempt to do so would result in immediate GPU hangs, presumably due
to the driver uploading an empty program with no EOT message.

NOTE: This is a candidate for the 8.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-01-18 00:45:00 -08:00
Kenneth Graunke
d56ad273c0 mesa: Support GL_VERTEX_ATTRIB_ARRAY_INTEGER in GL 3.0 contexts.
According to Table 6.8 (Page 348) in the OpenGL 3.0 specification,
glGetVertexAttribiv supports GL_VERTEX_ATTRIB_ARRAY_INTEGER.

NOTE: This is a candidate for the 8.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-01-18 00:45:00 -08:00
Vadim Girlin
b69728cba5 r600g: fix UINT_TO_FLT on evergreen
It should be processed as trans-only.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-18 08:03:41 +00:00
Chad Versace
a6dd4bf5fc i965/gen5: Fix rendering of depth buffers without stencil [v2]
Fixes the following OGLConform tests on gen5:
    depth-stencil(misc.state_on.depth_int)
    fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)

The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.

This bug was introduced by:
    commit d84a180417
    Author: Eric Anholt <eric@anholt.net>
    i965: Base HW depth format setup based on MESA_FORMAT, not bpp.

v2: Deref 'intel' directly. Move the branch for newer chipset to top.
    Quote the PRM. As requested by Ken.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <xunx.fang@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-17 17:26:45 -08:00
Anuj Phogat
ce1c949b16 intel: Return if pointer to intel_context is null
It is better to test if(intel == NULL) and simply return in that case.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-17 16:58:38 -08:00
Alex Deucher
46ce25722b r600g: add workaround for original R600 PS setup
The original R600 requires the UNCACHED_FIRST_INST bit
to be set in the PS.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Note: this is candidate for the stable branches.
2012-01-17 18:46:46 -05:00
Paul Berry
c03ad08e8d i965: Add .gitignore file to exclude automake build artifacts from git.
With the conversion to automake in commit
e326480e4e, several additional build
artifacts are created:

  src/mesa/drivers/dri/i965/.deps/
  src/mesa/drivers/dri/i965/.libs/
  src/mesa/drivers/dri/i965/Makefile
  src/mesa/drivers/dri/i965/Makefile.in
  src/mesa/drivers/dri/i965/i965_dri.la
  src/mesa/drivers/dri/i965/i965_symbols_test

This patch adds all of these files to .gitignore.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-01-17 15:44:26 -08:00
Anuj Phogat
f1a9a9bcd1 mesa: Add condition in glGetTexImage for zero size textures
TestMipMaps() function in src/OGLconform/textureNPOT.c calls glTexImage2D()
with width = 0. Texture with zero size skips miptree allocation due to a
condition in function _mesa_store_teximage3d(). While calling glGetTexImage()
it results in assertion failure in intel_map_texture_image() due to null mt
pointer.

This patch fixes the issue by detecting the zero size texture early in
glGetTexImage and glGetCompressedTexImage functions. In such a case function
simply returns doing nothing.
Verified that below mentioned bug is fixed by this patch.

https://bugs.freedesktop.org/show_bug.cgi?id=42334

NOTE: This is a candidate for stable branches

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-01-17 15:14:44 -08:00
Alex Deucher
94556f3594 radeon: share common fog code between radeon and r200
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-01-17 18:09:25 -05:00
Alex Deucher
e77c495d09 radeon: fix fog coordinate emit
Noticed by dungeon on phoronix:
http://phoronix.com/forums/showthread.php?65408-Radeon-R100-R200-Mesa-Driver-Sees-Attention&p=247018#post247018

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Note: this is a candidate for the stable branches.
2012-01-17 18:03:28 -05:00
Alex Deucher
afdd6f8c34 r200: fix fog coordinate emit
Noticed by dungeon on phoronix:
http://phoronix.com/forums/showthread.php?65408-Radeon-R100-R200-Mesa-Driver-Sees-Attention&p=247018#post247018

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Note: this is a candidate for the stable branches.
2012-01-17 18:03:28 -05:00
Dave Airlie
ba59a1a0d8 r600g: fix recip_uint on r600.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-18 06:53:02 +10:00
Vadim Girlin
7383e754b7 r600g: fix USLT for r600-eg 2012-01-17 15:25:12 -05:00
Alexander von Gluck IV
183133271c scons: Don't set visibility to hidden on Haiku
The Haiku swrast driver is out of tree.
2012-01-17 20:02:41 +00:00
Alexander von Gluck IV
64ae209d50 scons: Add Haiku build support
Enables building stock Mesa under the Haiku operating system.
2012-01-17 20:01:14 +00:00
Vadim Girlin
4ba4853c0a r600g: rework IDIV/UDIV and implement MOD/UMOD (v2)
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-17 19:53:20 +00:00
Eric Anholt
7fa5c919b0 mesa: Enable silent automake rules when available.
Finally, a quiet build for the i965 driver, at least!  (Note, you can
still get verbose builds at build-time by saying "make V=1")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-01-17 10:35:24 -08:00
Eric Anholt
e326480e4e i965: Convert the build to using automake.
This does introduce a warning by the automake build system, that the
missing-symbols test build is non-portable.  That's true -- Mac OS X
can't take something built as a loadable module and just link it as a
library.  Of course, we aren't building this on OS X at all, so it
would be nice to be able to suppress it, but I haven't found a way.

Still, the build is going to be much quieter than we have ever had
before, so I think this is a fair tradeoff until we find a way to shut
that warning up.

v2: Put a link in /lib to avoid transition pains for people.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
2012-01-17 10:35:24 -08:00
Eric Anholt
a14582d7e2 intel: Drop the version override code now that we don't have any left.
Fixes a compiler warning.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-17 10:35:24 -08:00
Eric Anholt
ccf0d31a21 intel: Fix warnings of undefined ffs().
For some reason these started showing up with the automake conversion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-17 10:35:24 -08:00
Scott Moreau
e0897009f8 Complete ARGB8888 naming convention format renames missed 2012-01-17 10:36:12 -05:00
Chad Versace
7e08bf08d1 i965: Fix gen6,gen7 when used with a non-HiZ capable DDX
Nothing works if HiZ is enabled and the DDX is incapable of HiZ (that is,
the DDX version is < 2.16).

The problem is that the refactoring that eliminated
intel_renderbuffer::stencil_rb broke the recovery path in
intel_verify_dri2_has_hiz().  Specifically, it broke line
intel_context.c:1445, which allocates the region for
DRI_BUFFER_DEPTH_STENCIL. That allocation was creating a separate stencil
miptree, despite the buffer being a packed depthstencil buffer. Havoc
ensued.

This patch introduces a bool flag that prevents allocation of that stencil
miptree.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44103
Tested-by: Ian Romanick <idr@freedesktop.org>
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-16 16:38:36 -08:00
Vinson Lee
8e543cc098 softpipe: Silence unused variable warning on non-LLVM builds.
Fix this GCC warning with non-LLVM builds.
sp_screen.c: In function ‘softpipe_get_shader_param’:
sp_screen.c:141:28: warning: unused variable ‘sp_screen’ [-Wunused-variable]

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-01-16 16:13:51 -08:00
Anuj Phogat
dd7220652e intel: Fix segfault in glXSwapBuffers with no bound context
Calling glXSwapBuffers with no bound context causes segmentation
fault in function intelDRI2Flush. All the gl calls should be
ignored after setting the current context to null. So the contents
of framebuffer stay unchanged. But the driver should not seg fault.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44614

Reported-by: Yi Sun <yi.sun@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Yi Sun <yi.sun@intel.com>
2012-01-16 15:07:17 -08:00
Vinson Lee
6fe133889c llvmpipe: Remove unused variable 'packed' from lp_test_round.
Fix this GCC warning.
lp_test_round.c: In function ‘test_round’:
lp_test_round.c:126:13: warning: variable ‘packed’ set but not used
[-Wunused-but-set-variable]

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-01-16 12:44:06 -08:00
Vinson Lee
eeff1ee746 util: Silence GCC unused-but-set-variable warning.
Fix this GCC 4.6 warning with 64-bit builds.
u_debug_stack.c: In function ‘debug_backtrace_capture’:
u_debug_stack.c:45:17: warning: variable ‘frame_pointer’ set but not
used [-Wunused-but-set-variable]

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-01-16 12:41:55 -08:00
José Fonseca
455090c4c4 vl: Make array initialization portable.
Should fix MSVC build.
2012-01-16 12:21:40 +00:00
Stéphane Marchesin
23d4a0569d i915g: Fix the blending for the A8 destination buffer case.
The i915 GPU can't do A8 dst, so we abuse GREEN8 buffers for that
purpose. However, things get hairy as we start to do blending,
because then GL_DST_*_ALPHA should be replaced with GL_DST_*_COLOR.
This is what we do here.

Fixes piglt fbo-alpha.
2012-01-15 23:39:49 -08:00
Matt Turner
6e9478e382 r200: remove left-over EGL_SOURCES variable
Rest was removed in 2a928899e.

Signed-off-by: Matt Turner <mattst88@gmail.com>
2012-01-15 12:09:52 -05:00
Dave Airlie
850021f225 r600g: fix mullo_uint trans slot only on r600/r700
This fixes 8 piglit tests that currently assert.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-15 16:53:41 +00:00
Vadim Girlin
91d4729696 r600g: implement clip distances
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-15 16:19:42 +00:00
Vadim Girlin
725a820b92 r600g: implement two-sided lighting (v3)
v2: select the colors in the pixel shader

v3: fix rs state creation for pre-evergreen

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-15 16:19:41 +00:00
Vadim Girlin
d84ab821c5 r600g: add support for ISHR/USHR/SHL on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:59 +00:00
Vadim Girlin
332e1d6d84 r600g: implement IDIV/UDIV on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:59 +00:00
Vadim Girlin
42539d569a r600g: implement ISSG on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:58 +00:00
Vadim Girlin
6b44470bb2 r600g: implement IABS on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:58 +00:00
Vadim Girlin
beb297f284 r600g: implement F2U on evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:58 +00:00
Vadim Girlin
5d97c5033b r600g: add FLT_TO_UINT opcode for evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:57 +00:00
Vadim Girlin
a9302de4a3 r600g: fix F2I on evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-01-15 16:04:57 +00:00
Christian König
2eabd05b75 vl: fix YV12 handling
We actually implemented YV21 instead of YV12, so fix the plane ordering.

Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-01-15 12:40:44 +01:00