Samuel Pitoiset
129d58e813
radv/ci: update list of flakes for VANGOGH
...
This one is already skipped in radv-skips.txt.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25656 >
2023-10-11 15:39:11 +00:00
Samuel Pitoiset
ede0502b4a
radv/ci: update list of expected failures on RAVEN
...
These have been fixed a while ago but I think only a subset of CTS
is used on RAVEN.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25656 >
2023-10-11 15:39:11 +00:00
Rhys Perry
15a3515d0b
aco/tests: test that hazards are resolved at the end of shader parts
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rhys Perry
690cb0b211
aco: resolve all possible hazards at the end of shader parts
...
fossil-db (vega10):
Totals from 1266 (2.01% of 63055) affected shaders:
Instrs: 707116 -> 708382 (+0.18%)
CodeSize: 3512452 -> 3517516 (+0.14%)
Latency: 6661724 -> 6666788 (+0.08%)
InvThroughput: 4393626 -> 4393904 (+0.01%); split: -0.00%, +0.01%
fossil-db (navi10):
Totals from 1305 (2.07% of 63015) affected shaders:
Instrs: 719699 -> 722009 (+0.32%)
CodeSize: 3650836 -> 3660076 (+0.25%)
Latency: 5691633 -> 5693933 (+0.04%)
InvThroughput: 1532010 -> 1532024 (+0.00%); split: -0.00%, +0.00%
fossil-db (navi31):
Totals from 1580 (1.99% of 79332) affected shaders:
Instrs: 1678242 -> 1679879 (+0.10%)
CodeSize: 8463464 -> 8470168 (+0.08%)
Latency: 14273661 -> 14275298 (+0.01%)
InvThroughput: 3668049 -> 3668080 (+0.00%); split: -0.00%, +0.00%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rhys Perry
e4842c0270
aco: consider exec_hi in reads_exec()
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rhys Perry
ed3ca5b781
aco: fix s_setreg hazards
...
s_setreg doesn't have any definitions.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rhys Perry
ce27875f09
aco: only mitigate VcmpxExecWARHazard when necessary
...
fossil-db (navi10):
Totals from 5059 (8.03% of 63015) affected shaders:
Instrs: 7384947 -> 7351196 (-0.46%)
CodeSize: 39393180 -> 39299196 (-0.24%); split: -0.28%, +0.04%
Latency: 119683018 -> 119585224 (-0.08%); split: -0.08%, +0.00%
InvThroughput: 29647188 -> 29623895 (-0.08%); split: -0.08%, +0.00%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rhys Perry
a73f76750b
aco: fix LdsDirectVMEMHazard WaW with the wrong waitcnt
...
Seems we missed this case.
fossil-db (navi31):
Totals from 24 (0.03% of 79332) affected shaders:
Instrs: 3562 -> 3538 (-0.67%)
CodeSize: 18740 -> 18644 (-0.51%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Fixes: 2cdb3e4b6b
("aco: add VMEMtoScalarWriteHazard tests")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374 >
2023-10-11 15:14:04 +00:00
Rohan Garg
26c2c96d62
anv: enable FCV for Gen12.5
...
Now that we have proper handling of FCV_CCS_E everywhere, we can turn
this on for Gen12.5.
This helps fix a performance regression where enabling fast
clears to non-zero values with CCS_E caused additional partial resolves,
regressing performance on certain games. Performance is helped on the
following games:
- F1'22: +45%
- RDR2: +6%
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589 >
2023-10-11 12:18:15 +00:00
Rohan Garg
8688a3b8f7
anv: ensure that FCV_CCS_E fast clears are properly tracked
...
Surfaces with FCV_CCS_E aux usage should be marked as fast cleared when
being rendered to, to ensure proper fast clear state tracking. We also
need to ensure that we're not trying to partially resolve surfaces with
level > 0 and layer > 0 since we don't track fast clear states for
those.
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589 >
2023-10-11 12:18:15 +00:00
Rohan Garg
300c98dbb2
intel/genxml: fix 3DSTATE_3D_MODE length to align with BSpec
...
Closes : #8632
Fixes: 569afd37f1
('intel/genxml: Copy gen12.xml to gen125.xml')
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589 >
2023-10-11 12:18:15 +00:00
Lionel Landwerlin
29352b304b
anv: add support for VK_EXT_nested_command_buffer
...
Our implementation of secondary command buffers already jumps into
them and edits the end of the secondary command buffer to jump back
into the primary.
That implementation can work just the same with any levels of
secondary. The only possible issue would happen with a secondary
calling itself, but that's not possible.
We also cannot support simultaneous execution with self-modifying
command buffers. That's actually not a problem at the moment because
we don't have multiple queues of the same family but we choose to
reflect that in the feature bits.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600 >
2023-10-11 11:32:47 +00:00
Lionel Landwerlin
8a12286214
anv: rename primary in container in ExecuteCommands()
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600 >
2023-10-11 11:32:47 +00:00
Lionel Landwerlin
798130b8aa
vulkan: bump headers/registry to 1.3.267
...
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600 >
2023-10-11 11:32:47 +00:00
Lucas Stach
1e80011bc7
Revert "ci/etnaviv: allow failure on failing test"
...
This reverts commit 2ac2268ce7
, as the issue causing the
test to fail has been resolved.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25646 >
2023-10-11 11:17:28 +00:00
Lucas Stach
aeb6584ecd
etnaviv: fix read staging buffer leak
...
Currently we only free a potentially allocated staging buffer
when the mapping is a write mapping, but staging buffers can
also be allocated for read mappings. Fix the read staging
buffer leaks by always freeing the staging buffer.
Closes #9967
Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de >
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com >
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25646 >
2023-10-11 11:17:28 +00:00
Matt Coster
c619d9c1b6
pvr: Clean up & fix sampler border color support
...
Take advantage of some vk_sampler goodness and migrate all pvr
tex_formats to map to pipe_formats in pvr_formats.c. This allows us to
get rid of all the nasty manual packing functions.
This cleanup incidentally fixes some bad swizzling that was happening
in the manual handling.
Fixes: 4a2e6284
pvr: Add support for sampler border colors
Signed-off-by: Matt Coster <matt.coster@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25270 >
2023-10-11 10:58:34 +00:00
Matt Coster
efb9b03637
pvr: Use vk_sampler base
...
Signed-off-by: Matt Coster <matt.coster@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25270 >
2023-10-11 10:58:33 +00:00
Matt Coster
a92d536cd7
pvr: Switch to common pipeline cache implementation
...
We don't currently make use of pipeline caching, but the common
implementation handles the boilerplate we had in pvr_pipeline_cache.c
for us.
Signed-off-by: Matt Coster <matt.coster@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25422 >
2023-10-11 10:41:43 +00:00
Danylo Piliaiev
2717499c91
tu: Disable preamble push consts when they are not used
...
It's a common case for Zink which has to declare push consts in
pipeline layout, even if they are not actually used in shaders, due
to the compatibility rules.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25641 >
2023-10-11 09:40:21 +00:00
Karmjit Mahil
8f59274e22
pvr: Fix PPP_SCREEN sizes
...
The `- 1` was accidentally removed.
Fixes: aae23fe68d
("pvr: HWRT creation simplifications.")
Reported-by: Frank Binns <frank.binns@imgtec.com >
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
df57840dd0
pvr: Fix SPM load shader sample rate
...
Reported-by: James Glanville <james.glanville@imgtec.com >
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
41a9af4819
pvr: Refactor subpass ds and sample count setup
...
Now we first check the sample count from the ds attachment as well
as setting it up.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
e07cff4ac5
pvr: Fix subpass sample count on ds attachment only
...
When no color attachments were used in a subpass, the sample count
was left unchanged to `1` while we should instead have picked it
up from the ds attachment if there was one.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
bfcb88ea99
pvr: Order tile buffer EOT emits to be last
...
Tile buffer emits required a load from the tile buffer into the
output regs, so they must be placed at the end of the EOT program
as to not corrupt the output register emits.
This commit orders the emit state to place output register emits
first, and tile buffer emits last.
dEQP test fixed:
dEQP-VK.renderpass.suballocation.attachment.4.422
... and others from the dEQP-VK.renderpass.suballocation.*
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
9d1fc4de72
pvr: Fix OOB access of pbe_{cs,reg}_words
...
`hw_render->eot_surface_count` also includes surface which don't
need an emit. Using `i` was leading to OOB access when there were
surfaces that didn't need emits, and in total there were
`> PVR_MAX_COLOR_ATTACHMENTS` surfaces.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
e5feea3826
pvr: Fix pbe_emit assert
...
The `eot_surface_count` also includes surfaces which don't need an
emit. Surfaces with PVR_RESOLVE_TYPE_TRANSFER don't need an emit
since they'll be resolved through a transfer op, but they still count
against the total, thus the assert was incorrect.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Karmjit Mahil
e6c1e0e518
pvr: Fix MRT index in PBE state
...
The same MRT index was incorrectly being set for all render
targets, in the PBE state.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584 >
2023-10-11 08:19:30 +00:00
Faith Ekstrand
65f12fde44
nvk: Improve address space and buffer size limits
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:57:10 -05:00
Faith Ekstrand
b0d0c2d765
nvk: Always emit at least one color attachment
...
Without this, alpha to coverage doesn't work because the hardware
ignores the output of the first color from the shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:58 -05:00
Faith Ekstrand
e9747eb91f
nvk: Disable depth or stencil tests when unbound
...
Dynamic rendering requires that the client be able to bind just one
aspect of a depth/stencil image. Because we only have interleaved
depth/stencil on NVIDIA and no actual disable bits, this means we need
to implicitly AND any enables with a vk_format != UNDEFINED check. In
future, we might want to do that with a macro but we'll keep it simple
for today.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:38 -05:00
Faith Ekstrand
6ab969ff4a
nil/format: Advertise R10G10B10A2_UINT texture buffer support
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:28 -05:00
Faith Ekstrand
7bedd0c2fc
nil/format: Use A for alpha blend
...
This lets us reserve B for buffer.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:21 -05:00
Faith Ekstrand
1c4d5135a6
nvk: Reset descriptor pool allocator when all sets are destroyed
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:14 -05:00
Faith Ekstrand
9a51185d45
nvk: Set max descriptors to 2^20 for most descriptor types
...
Dynamic is the exception here. Those have much stricter limits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:56:04 -05:00
Faith Ekstrand
3d3641e446
nvk: Emit MME_DMA_SYSMEMBAR before indirect draw/dispatch
...
This fixes issues where we may read stale data from other parts of the
GPU when we go to do an indirect draw fetch.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:55:56 -05:00
Faith Ekstrand
160bf37bc4
nvk: Advertise more inline uniform block limits
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653 >
2023-10-11 02:55:44 -05:00
Eric Engestrom
9c2b523c53
ci/b2c: use latest mesa-trigger image
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25643 >
2023-10-11 06:37:20 +00:00
Eric Engestrom
298f2db76d
ci/b2c: move to the shiny new gfx-ci/ci-tron
repo
...
We've successfully moved the repo to its new location now that the
project is ready for general use.
Update the config to use the new paths.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25643 >
2023-10-11 06:37:19 +00:00
Karol Herbst
7afdbd5f6d
nir/load_libclc: fix libclc memory leak
...
Fixes: ef453f5439
("spirv: Add a shared libclc loader")
Signed-off-by: Karol Herbst <kherbst@redhat.com >
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25649 >
2023-10-11 03:05:23 +00:00
Qiang Yu
a59a66e111
radeonsi: disable disk cache when use aco
...
This is a temp fix. Currently we mix use llvm and aco to compile
shaders when AMD_DEBUG=useaco, but disk cache need function
identifier when creation, aco compiled shader should not use llvm
function identifier, so we have to disable disk cache when use
aco for now.
After aco is able to compile all shaders, we can re-enable disk
cache by removing the llvm function identifier when aco.
Fixes: d1dd36a74e
("radeonsi: be able to use aco compiler for mono ps")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9673
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Signed-off-by: Qiang Yu <yuq825@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25607 >
2023-10-11 02:36:29 +00:00
Mike Blumenkrantz
e8a76adde8
lavapipe: don't block begin/end cmdbuf pipeline barriers
...
these are now useful
fixes #9972
Fixes: 3b547a9b58
("lavapipe: Switch to the common sync framework")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25652 >
2023-10-11 01:34:42 +00:00
Mike Blumenkrantz
7078cd3652
zink: set ZINK_DEBUG=quiet for polaris jobs
...
modifiers aren't supported here, so this will otherwise spam infinitely
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25645 >
2023-10-10 23:12:17 +00:00
Mike Blumenkrantz
eb94d235fb
zink: apply ZINK_DEBUG=quiet to all missing feature warnings
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25645 >
2023-10-10 23:12:17 +00:00
Dave Airlie
833f04d261
lavapipe + docs: update ycbcr extension enables.
...
This passes all the dEQP-VK.ycbcr* tests and updates the docs.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25628 >
2023-10-11 05:54:14 +10:00
Karol Herbst
119c213087
rusticl/memory: fix potential use-after-free in clEnqueueSVMMemFill
...
Fixes: bfee3a8563
("rusticl: add support for fine-grained system SVM")
Signed-off-by: Karol Herbst <kherbst@redhat.com >
Reported-by: @LingMan <18294-LingMan@users.noreply.gitlab.freedesktop.org >
Reviewed-by: @LingMan <18294-LingMan@users.noreply.gitlab.freedesktop.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25637 >
2023-10-10 18:41:48 +00:00
Frank Binns
a157ab7b33
pvr: emit PPP state when vis_test dirty bit is set
...
Unlike other dirty bits, the vis_test dirty bit wasn't being taken into
consideration when determining whether PPP state needed to be emitted as part
of a draw call.
Fixes a large number of tests in dEQP-VK.query_pool.occlusion_query.*.
Fixes: 2b1992a000
("pvr: Implement vkCmdBeginQuery API.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25491 >
2023-10-10 18:27:01 +00:00
Frank Binns
a44ec36684
pvr: fix setup of load op unresolved msaa mask
...
Bits were being assigned rather than ORed into the mask during setup. Noticed
through code inspection.
Fixes: e089166776
("pvr: Add support for VK_ATTACHMENT_LOAD_OP_LOAD.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25487 >
2023-10-10 18:10:52 +00:00
Frank Binns
ae277edc3a
pvr: change a few places to use PVR_DW_TO_BYTES()
...
Signed-off-by: Frank Binns <frank.binns@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25489 >
2023-10-10 17:54:14 +00:00
Frank Binns
6417a65f28
pvr: fix allocation size of clear colour consts shared regs buffer
...
The number of const shared registers was being used for the allocation size
rather than the number of bytes. In practice this doesn't make a difference as
the max allocation size is 24 bytes, which then gets rounded up to 64 bytes by
the buffer allocation function. However, we might as well make the allocation
size correct to avoid any future confusion. Noticed through code inspection.
Fixes: 7509e259f8
("pvr: Implement color/depth/depth+stencil attachment clear.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com >
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25489 >
2023-10-10 17:54:14 +00:00