Commit Graph

23 Commits

Author SHA1 Message Date
Eric Anholt
0cade4de4f intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time.  Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
2008-10-28 13:23:33 -07:00
Brian Paul
ecadb51bbc mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template 2008-09-18 15:17:05 -06:00
Eric Anholt
35fd72756a intel: track move of bo_exec from drivers to bufmgr. 2008-09-10 13:59:45 -07:00
Dave Airlie
f75843a517 Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c.
2008-08-24 17:59:10 +10:00
Dave Airlie
7c81124d7c Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-24 17:52:40 +10:00
Eric Anholt
53675e5c05 Merge branch 'drm-gem'
Conflicts:

	src/mesa/drivers/dri/intel/intel_span.c
	src/mesa/main/fbobject.c

This converts the i915 driver to use the GEM interfaces for object management.
2008-08-08 15:32:24 -07:00
Xiang, Haihao
8e8019b49a dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646 2008-08-05 11:34:26 +08:00
Eric Anholt
902e401a38 intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.
Fixes oglconform rbGetterFuncs testcase.  The span code for this mode hasn't
actually been tested.
2008-07-26 17:39:23 -07:00
Eric Anholt
2e37143800 intel: Add a little span cache to spead up readpixels by cutting syscalls. 2008-07-23 10:21:25 -07:00
Eric Anholt
d2d5abfaeb intel-gem: Use pread/pwrite for span access.
This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
2008-07-23 10:21:25 -07:00
Eric Anholt
bdaa06ad63 intel: move renderbuffer mapping to separate functions.
This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish.  Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
2008-07-23 10:21:24 -07:00
Eric Anholt
a5f02368d2 intel-gem: Disable spantmp sse/mmx functions when tile swizzling.
Those functions rely on being able to treat the GET_PTR returned value as an
array indexed by x, but that's not the case for our tiling.

Bug #16387
2008-07-15 13:21:37 -07:00
Eric Anholt
2e841880cf drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. 2008-07-11 18:58:19 -07:00
Eric Anholt
def6e4f420 intel: span rendering requires just a flush before starting, not finish.
The dri_bo_map()s that follow will take care of idling the hardware as needed.
2008-07-02 11:49:10 -07:00
Eric Anholt
4b3ed4d2d1 intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
Apparently in Y mode we get bit 6 ^ bit 9.  The reflect demo in 'd' mode now
displays correctly.
2008-07-02 10:21:44 -07:00
Eric Anholt
19f585a3cf intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode.  Instead, guess the correct
tiling in screen setup.

Also, fix the Y-tiling pitch setup.  The pitch to the next tile in Y is
32 scanlines, not 8.
2008-07-02 09:10:21 -07:00
Eric Anholt
e74f54793e intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.
It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling.  It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
2008-07-01 16:14:08 -07:00
Eric Anholt
e2baf564d1 [intel-gem] Bug #16326: Fix X tile unswizzling on 965.
Apparently a bit gets flipped in the addressing for some rows of each tile.
2008-06-17 11:18:02 -07:00
Keith Packard
537bbe6dec [intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
2008-05-06 10:51:08 -07:00
Xiang, Haihao
c30392f187 i965: fix segfault caused by commit e131c46b20. 2008-01-10 16:45:35 +08:00
Brian
ff73c783cc Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.
These fields are no longer indexed by shader output.  Now, we just have
a simple array of renderbuffer pointers.

If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers.  Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.

A few more changes and simplifications can follow from this...
2008-01-06 10:43:20 -07:00
Eric Anholt
7c71ef3a3d [intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes.  It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965).  The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-12 11:52:10 -08:00
Eric Anholt
77a5bcaff4 [intel] Move over files that will be shared with 965-fbo work. 2007-11-09 14:27:33 -08:00