Commit Graph

200043 Commits

Author SHA1 Message Date
Mary Guillemard
5f8addfd99 util/bitpack_helpers: Make fixed packs CL safe
We emulate roundf and llroundf for compatibility.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32939>
2025-01-08 11:37:27 +00:00
Mary Guillemard
bd872e2aaa util/bitpack_helpers: Use UINT64_MAX instead of ~0ULL
This fixes issues with LLVM on OpenCL C failing to represent 128-bit
integers.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32939>
2025-01-08 11:37:27 +00:00
Boris Brezillon
9ba38350de panvk/jm: Fix depth clipping with small viewport depth range
Same as 7ca01506c9 ("panvk: hack to improve depth clipping with
small viewport depth range") but applied to the JM backend.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Benjamin Lee <benjamin.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32905>
2025-01-08 11:13:18 +00:00
Boris Brezillon
3b6f0ce032 panvk: Don't invalidate the viewport on cull mode updates
vk_rasterization_state_depth_clip_enable() checks the clip and clamp
modes, not the cull mode. RS_DEPTH_CLIP_ENABLE got confused with
RS_CULL_MODE in 7ca01506c9 ("panvk: hack to improve depth clipping
with small viewport depth range").

Fixes: 7ca01506c9 ("panvk: hack to improve depth clipping with small viewport depth range")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Benjamin Lee <benjamin.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32905>
2025-01-08 11:13:18 +00:00
Friedrich Vock
71392fff25 aco: Fix dead instruction/index handling for try_insert_saveexec_out_of_loop
The loop checking if exec is overwritten didn't check for NULL
instructions, and didn't fix up reg write indices after inserting
instructions.

Fixes: fcd94a8c ("aco: move try_optimize_branching_sequence() to postRA optimizations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32746>
2025-01-08 10:48:01 +00:00
Georg Lehmann
67d74a04b9 nir/peephole_select: allow load_vector/scalar_arg_amd
Foz-DB Navi21:
Totals from 1507 (1.90% of 79395) affected shaders:
MaxWaves: 31830 -> 31870 (+0.13%); split: +0.20%, -0.08%
Instrs: 938704 -> 937232 (-0.16%); split: -0.19%, +0.03%
CodeSize: 4970860 -> 4964652 (-0.12%); split: -0.14%, +0.02%
VGPRs: 79536 -> 79512 (-0.03%); split: -0.08%, +0.05%
Latency: 5194524 -> 5218285 (+0.46%); split: -0.38%, +0.84%
InvThroughput: 1200152 -> 1207251 (+0.59%); split: -0.02%, +0.61%
VClause: 20728 -> 20741 (+0.06%); split: -0.11%, +0.17%
SClause: 33612 -> 32871 (-2.20%); split: -2.78%, +0.57%
Copies: 70601 -> 68847 (-2.48%); split: -2.62%, +0.13%
Branches: 20032 -> 17521 (-12.53%)
PreSGPRs: 47828 -> 47801 (-0.06%)
VALU: 637446 -> 638094 (+0.10%); split: -0.02%, +0.13%
SALU: 88627 -> 88462 (-0.19%); split: -1.08%, +0.90%
VMEM: 36664 -> 36659 (-0.01%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32792>
2025-01-08 09:56:39 +00:00
Georg Lehmann
208d8cd715 radv: run peephole_select in optimize_nir_algebraic
Foz-DB Navi21:
Totals from 451 (0.57% of 79395) affected shaders:
MaxWaves: 8680 -> 8616 (-0.74%)
Instrs: 689610 -> 688225 (-0.20%); split: -0.21%, +0.01%
CodeSize: 3524580 -> 3521740 (-0.08%); split: -0.11%, +0.03%
VGPRs: 28512 -> 28584 (+0.25%)
Latency: 1906219 -> 1892124 (-0.74%); split: -0.91%, +0.17%
InvThroughput: 481931 -> 483570 (+0.34%); split: -0.00%, +0.34%
VClause: 10317 -> 10296 (-0.20%)
SClause: 18105 -> 18088 (-0.09%); split: -0.17%, +0.07%
Copies: 69532 -> 67579 (-2.81%); split: -2.85%, +0.04%
Branches: 21353 -> 20501 (-3.99%)
PreSGPRs: 27004 -> 27005 (+0.00%)
VALU: 436235 -> 436334 (+0.02%); split: -0.01%, +0.03%
SALU: 102349 -> 101944 (-0.40%); split: -0.61%, +0.21%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32792>
2025-01-08 09:56:39 +00:00
Christian Gmeiner
b6ef9017f4 etnaviv: isa: Support src2 for texldb and texldl
We need to add variants of these instructions, which are used with a shadow
samper and passed the shadow reference value via src2.

Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
2025-01-08 07:57:39 +00:00
Christian Gmeiner
5daa47c1f8 etnaviv: isa: Support src2 for texld
We need to add a variant of the texld instruction, which is used with a shadow
samper and passed the shadow reference value via src2.

Blob generates such texld's for deqp's GLES3.functional.texture.shadow.2d.* (GC3000).
Fixes spec@arb_depth_texture@texdepth.

Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
2025-01-08 07:57:39 +00:00
Lucas Stach
9e71829bcf etnaviv: isa: fix typo in SRC2_USE map
Fixes: b216fd044b ("etnaviv: isa: Add encode support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
2025-01-08 07:57:39 +00:00
Kenneth Graunke
35f175301d brw: Fix vectorizer hole_size condition after signedness change
Marek recently changed hole_size to be signed, rather than unsigned.
A negative hole_size means that the two loads overlap - and thus are
prime candidates to be combined.

My original hole_size handling was:

   if hole_size > 4 * (8 - low->num_components) then don't vectorize

For non-overlapping loads, this worked: NIR's largest vector is vec16,
and if low was already a vec16, combining it with anything would exceed
that, so it'd never be considered.  That meant low would always be a
vec8 or less, so (8 - low->num_components) was a positive number.

Now that we see overlapping loads, we can see a vec16 low, vec4 high,
and also a negative hole size, giving us fun comparisons like:

   -16 > 4 * (8 - 16)   =>   -16 > -32   => true, don't vectorize

Which is absolutely the wrong thing to do, because the high load's data
is entirely included within the former load's data.

The idea here was to make sure the second load would be able to pack at
least one component into the first's V8 result.  But even this isn't the
best, because...even if it's simply adjacent, doing one V16 load is more
efficient than requesting two back to back V8 loads.

So, we just simplify down to a static check: if there's an entire V8 of
hole, don't vectorize.  This already won't happen because the core pass
has max_hole set to 28 bytes (7 32-bit components), but that could
change based on the needs of other drivers, so let's be defensive.

fossil-db results on Alchemist:

   Instrs: 161533978 -> 161295137 (-0.15%); split: -0.20%, +0.05%
   Subgroup size: 8092544 -> 8092568 (+0.00%)
   Send messages: 7915233 -> 7844503 (-0.89%); split: -0.94%, +0.05%
   Cycle count: 16577700697 -> 16702609256 (+0.75%); split: -0.59%, +1.35%
   Spill count: 72338 -> 67226 (-7.07%); split: -7.36%, +0.29%
   Fill count: 134058 -> 125980 (-6.03%); split: -6.83%, +0.80%
   Scratch Memory Size: 4092928 -> 3786752 (-7.48%); split: -7.53%, +0.05%
   Max live registers: 33031460 -> 32945994 (-0.26%); split: -0.27%, +0.01%
   Max dispatch width: 5778384 -> 5778536 (+0.00%); split: +0.26%, -0.26%
   Non SSA regs after NIR: 179809505 -> 152735471 (-15.06%); split: -15.08%, +0.03%

Fixes: c21bc65ba7 ("nir/opt_load_store_vectorize: make hole_size signed to indicate overlapping loads")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32932>
2025-01-08 00:19:54 +00:00
Sagar Ghuge
33d9a685a5 anv: Add pipelined coarse pixel state
3DSTATE_CPS_POINTERS is deprecated on PTL, so let's switch to
3DSTATE_COARSE_PIXEL to deliver CPS state as pipelined state.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32737>
2025-01-07 23:53:44 +00:00
Sagar Ghuge
9d33443d7b intel/genxml: Add coarse pixel related changes
This change adds CPS related new state instruction, structure and
enum.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32737>
2025-01-07 23:53:44 +00:00
Caio Oliveira
868016d92c intel/brw/xe2+: Do not use $.dst or $.src SWSB annotations in SENDs
When a SEND instruction is a EOT, the scoreboard lowering will not
allocate a new SBID for it, since nothing needs to wait for it.  In
Gfx12 this allowed the SEND to get out-of-order $.dst or $.src
dependencies.

Starting on Xe2+ this is not supported anymore, in favor of supporting
more combined modes.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32712>
2025-01-07 22:23:59 +00:00
Lucas Stach
a7d164e42b ci/etnaviv: drop gl-1.4-polygon-offset fail
Now that the offset unit is correctly scaled depending on
the depth buffer format, this test can be expected to pass.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32756>
2025-01-07 22:09:16 +00:00
Lucas Stach
98b3723208 etnaviv: fix polygon offset for 24bpp depth buffers
Currently we scale the polygon offset units with a fixed factor,
matching the MRD (minimal resolvable distance) for a 16bpp depth
buffer. This wastes a lot of precision when a 24bpp depth buffer
is used.

Apply the correct MRD scale, depending on the format of the
currently bound depth buffer.

Fixes piglit spec@!opengl 1.4@gl-1.4-polygon-offset.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32756>
2025-01-07 22:09:16 +00:00
Tapani Pälli
1cc17e9ce9 intel/compiler: take reg_unit size into account with ubo ranges
Fixes: 1ab4fe2dd6 ("brw: Don't shrink UBO push ranges in the backend")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12423
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32925>
2025-01-07 21:38:06 +00:00
Job Noorman
c3e7384bbb ir3: always set wrmask for movmsk
We failed to set the wrmask of movmsk expanded from ballot.macro. This
caused legalization to miss the need for (ss) when a component other
than the first is used.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 1a78604d20 ("ir3: Add support for subgroup arithmetic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32918>
2025-01-07 20:55:22 +00:00
Marek Olšák
c20c46cf7b ac: update ATOMIC_MEM definitions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32877>
2025-01-07 20:24:19 +00:00
Marek Olšák
f72a11f38d radeonsi: always use RADEON_USAGE_DISALLOW_SLOW_REPLY
All places are fine with getting a false negative as long as buffer_wait
returns quickly. This can improve performance.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32877>
2025-01-07 20:24:19 +00:00
Marek Olšák
271d5edf87 radeonsi: fix a perf regression due to slow reply from GEM_WAIT_IDLE for timeout=0
It sometimes takes 1 ms to return with timeout=0, which is unacceptable.

Fixes: 4194774edf - radeonsi: move barriers out of si_launch_grid_internal_ssbos

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32877>
2025-01-07 20:24:19 +00:00
Pierre-Eric Pelloux-Prayer
dd11eec06b gl/spirv: update subgroup_size if GroupNonUniform is used
This is similar to what link_intrastage_shaders is doing and it
fixes the following test:
   KHR-Single-GL46.subgroups.builtin_var.compute.subgroupsize_compute

Which was failing with SPIRV but passing with GLSL, the diff being:
 - SPIRV: "subgroup_size: 1"
 - GLSL:  "subgroup_size: 2"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32698>
2025-01-07 19:32:43 +00:00
Pierre-Eric Pelloux-Prayer
33affa7c36 radeonsi/tests: update results
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32698>
2025-01-07 19:32:43 +00:00
Pierre-Eric Pelloux-Prayer
dc293ffe50 radeonsi: fallback to util_blitter_draw_rectangle
The blitter VS expects coords to fit in a signed int16. When this
is not the case, use util_blitter_draw_rectangle instead.

Since util_blitter_draw_rectangle sets vertex elements, we need
to make sure they're properly restored.

The alternative to this fallback would be to pass coordinates
unpacked (so 4 SGPRs instead of 2), but this doesn't fix the
fbo-blit-check-limits test because of uv interpolation precision
issue.
Using 2 triangles instead of a rectangle + disabling
window_space_position helps but then this breaks some GLES3 tests,
like dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_x
(which doesn't pass either if u_blitter is used for all cases).

Using a single triangle covering the whole rectangles fixes all
cases but it then requires to setup scissors to not write too
much pixels...
So, instead of adding so much complexity, let's use u_blitter
for the "large coordinates" fallback, and keep the rectangle blit
for the other cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32698>
2025-01-07 19:32:43 +00:00
Samuel Pitoiset
7f50162424 radv: fix programming WALK_ALIGN8_PRIM_FITS_ST on GFX12
This also needs to be disabled when a VRS image is used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32914>
2025-01-07 18:56:24 +00:00
Samuel Pitoiset
d7bc370b9e radv: configure the VRS surface swizzle mode on GFX12
GFX11 allowed only one swizzle mode for the VRS image but GFX12 allows
all 2D non-linear swizzle modes and PC_SC_VRS_INFO needs to be
configured.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32914>
2025-01-07 18:56:24 +00:00
Samuel Pitoiset
0b53e645a0 radv: disable VRS coarse shading with 8x MSAA on GFX12
This isn't supported and the hw always clamps to 1x1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32914>
2025-01-07 18:56:24 +00:00
Juan A. Suarez Romero
c5954c4329 v3dv: check requirements for USAGE_INPUT_ATTACHMENT
If the format does not support COLOR_ATTACHMENT or DEPTH_STENCIL
features then it can't be used as an input attachment.

Fixes dEQP-VK.api.info.unsupported_image_usage.*.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32790>
2025-01-07 14:50:44 +00:00
Juan A. Suarez Romero
db249f24a6 vc4: initialize variable
While this is strictly not necessary, it fixes an apparent false
positive issue about reading garbage value detected by static analyzer.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32819>
2025-01-07 14:21:42 +00:00
Juan A. Suarez Romero
69d3d7288e v3dv: fix assigned value is garbage or undefined
This is actually a false positive detected by static analyzer, because
it assumes that `device->instance->meta_cache_enabled` can change
between two execution points.

In order to instruct static analyzer this is not the case, we assing it
to a local variable, and do the checks based on that.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32819>
2025-01-07 14:21:42 +00:00
Juan A. Suarez Romero
0d14e129bc v3d: avoid 0-size variable length array
Declaring a variable-length array (VLA) based on a variable that can be
0 is declared dangerous.

In this case, the variable can't take value 0, so adding an assertion
fixes the issue.

This was detected by static analyzer.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32819>
2025-01-07 14:21:42 +00:00
Samuel Pitoiset
f94bd67b82 aco: fix VS prologs on GFX12
MTBUF/MUBUF instructions must use zero for SOFFSET, use const_offset
instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32904>
2025-01-07 13:44:32 +00:00
Corentin Noël
55cd0fb42c virgl: Use MAX_SAMPLERS instead of MAX_SHADER_SAMPLER_VIEWS
The PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS cap is meant for samplers and not sampler
views, change this.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32706>
2025-01-07 13:15:47 +00:00
Corentin Noël
ab5084b054 virgl: Update virgl_hw.h from virglrenderer
Use the latest version and update the supported formats.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32706>
2025-01-07 13:15:46 +00:00
Job Noorman
b5c99e6f57 ir3/cp: swap back correct srcs when swap failed
While making the swapping code generic, the swap-back path was left as
is causing the wrong sources to be swapped.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 00656526d8 ("ir3/cp: extract common src swapping code")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32920>
2025-01-07 12:14:14 +00:00
Danylo Piliaiev
ac2046c5b0 tu/perfetto: Add app and engine names to the command buffer tracepoint
Makes possible to understand which app submitted a command buffer.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31550>
2025-01-07 11:44:41 +00:00
Danylo Piliaiev
5ae03b4aea tu/perfetto: Always emit submission event and time it
We previously missed submissions that don't sync timestamps.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31550>
2025-01-07 11:44:41 +00:00
Boris Brezillon
e55de285cc panfrost: Kill panfrost-job.h
It's empty now, so we don't need to include it from the packer headers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32899>
2025-01-07 11:10:55 +00:00
Boris Brezillon
c0f3bac826 panfrost: Move MAX_{MIP_LEVELS,IMAGE_PLANES} to pan_texture.h
This is where those macros are used, and those are the last two
definitions preventing us from dropping panfrost-job.h.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32899>
2025-01-07 11:10:55 +00:00
Boris Brezillon
e48f2da7da panfrost: Move MALI_EXTRACT_INDEX to pan_format.h
Move MALI_EXTRACT_INDEX to pan_format.h where all format-related macros
live and kill the unused MALI_EXTRACT_TYPE and MALI_FORMAT_COMPRESSED
macros.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32899>
2025-01-07 11:10:55 +00:00
Boris Brezillon
2fdbdc270b panfrost: Kill the uXX typedefs
We use uintXX_t most of the time, so let's be consistent and use the
stdint types everywhere instead of their shorter uXX variants.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32899>
2025-01-07 11:10:55 +00:00
Boris Brezillon
63fc0a2de9 panfrost: Kill the mali_ptr typedef
mali_ptr is no shorter than uint64_t, and we already have a few places
where we use uint64_t to store GPU virtual addresses in src/panfrost, so
let's just kill this typedef and use uint64_t types everywhere.

That's one step towards panfrost-job.h removal.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32899>
2025-01-07 11:10:55 +00:00
Feng Jiang
701600fb11 radv/rt: Fix memleak in radv_init_header()
Fixes: f8b584d ("vulkan/runtime,radv: Add shared BVH building framework")
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32887>
2025-01-07 09:49:56 +00:00
Samuel Pitoiset
c5fe9dcf16 ac/descriptors: fix configuring NBC views on GFX12
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32892>
2025-01-07 09:15:12 +00:00
Boris Brezillon
ae76a6a045 panvk: Pack push constants
We're about to add more sysvals, and the more we add, the bigger the
sysvals region gets, which increases the amount of memory we have to
allocate when push_uniforms are dirty.

Instead of allocating FAUs for all sysvals/push_constants, track FAU
usage per-shader, and pack those. This implies emitting an FAU buffer
per stage instead of trying to share it, but that's an acceptable
trade-off.

While at it, automate the sysval dirty tracking a bit.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00
Boris Brezillon
aa78fe7683 panvk: Pass a cmdbuf to blend_emit_descs()
Now that panvk_cmd_buffer.h is accessible from
src/panfrost/vulkan/panvk_vX_xxx.c files, there's no reason to pass
a gazillon arguments to blend_emit_descs(). We can just pass a cmdbuf
and let the helper extract the other parameters from there. It also
allows for extra automation, like dirtying the push_uniform buffer
when the new blend config reads the blend constant.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00
Boris Brezillon
ed55ab17db panvk: Factor-out the sysvals initialization logic
We're about to make the sysval logic a bit more complication when
introducing push constant packing. Let's first factor-out the sysvals
handling so the JM/CSF backend don't have to duplicate the thing.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00
Boris Brezillon
a6319f8951 panvk: Don't lower load_blend_const_color_rgba
We use blend shaders, so load_blend_const_color_rgba should
not be present in the fragment shader. We might want to re-introduce
this code if we decide to specialize fragment shaders when the
blend configuration is static, but let's drop it for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00
Boris Brezillon
2af6e4beeb pan: Don't pretend we support load_{vertex_id_zero_base,first_vertex}
load_vertex_id_zero_base() is supposed to return the zero-based
vertex ID, which is then offset by load_first_vertex() to get
an absolute vertex ID. At the same time, when we're in a Vulkan
environment, load_first_vertex() also encodes the vertexOffset
passed to the indexed draw.

Midgard/Bifrost have a sligtly different semantics, where
load_first_vertex() returns vertexOffset + minVertexIdInIndexRange,
and load_vertex_id_zero_base() returns an ID that needs to be offset
by this vertexOffset + minVertexIdInIndexRange to get the absolute
vertex ID. Everything works fine as long as all the load_first_vertex()
and load_vertex_id_zero_base() calls are coming from the
load_vertex_id() lowering. But as mentioned above, that's no longer
the case in Vulkan, where gl_BaseVertexARB will be turned into
load_first_vertex() and expect a value of vertexOffset in an
indexed draw context.

We thus need to fix the mismatch by introducing two new
panfrost-specific intrinsic so we can stop abusing load_first_vertex()
and load_vertex_id_zero_base().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00
Boris Brezillon
54033bc052 panvk: Fix first_vertex/base_instance types
gl_Base{VertexARB,Instance} are signed integers, so reflect that in
the types we declare in the sysval struct.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32415>
2025-01-07 08:15:19 +00:00