We were missing a couple of 4-bit formats, let's add them.
Vulkan 1.0 already requires VK_FORMAT_B4G4R4A4_UNORM_PACK16, which mapes
to PIPE_FORMAT_A4R4G4B4_UNORM, which we're currently missing support for.
But we can also support VK_FORMAT_R4G4B4A4_UNORM_PACK16, which maps to
PIPE_FORMAT_A4B4G4R4_UNORM. This format is optional, but there's no
reason we shouldn't expose support for it.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32083>
Without multiview, a shader that doesn't write to the any of the
extended FIFO attributes (pointsize and layer) can be used with either
FIFO format. This allows us to switch to the basic FIFO format when
using the no_psiz variant. In multiview vertex shaders, output offsets
depend on the FIFO format. Instead of trying to patch these in the
no_psiz variant, just don't do the optimization for now.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31704>
Two components to this: first we only issue fragment jobs for enabled
views. This prevents disabled layers from being cleared implicitly with
`LOAD_OP_CLEAR`, and also reduces overhead (these layers have no
primitives so the fragment job is wasted work). Second is hooking up the
view mask to vk_meta_clear.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31704>
In Valhall multiview, position/varying shaders are invoked once per
draw. Each invocation write separate outputs for all views. Fragment
processing is handled by the existing multilayer support. Note that
because the hardware only supports up to 8 views, we don't have to care
about the case where there are too many layers to fit in one tiler when
multiview is enabled.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31704>
In panvk we pass absolute view indices to the hardware, so we need to do
the conversion from compacted to absolute at some point. Emitting
absolute indices from nir_lower_multiview initially looks like the
simplest option, but nir_lower_io_to_temporaries will emit a write for
every element of array varyings. This results in unnecessary writes to
disabled views.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31704>
This is needed for implementing multiview in panvk, where the address
calculation for multiview outputs is not well-represented by lowering to
nir_intrinsic_store_output with a single offset.
The case where a variable is both per-view and per-{vertex,primitive} is
now unsupported. This would come up with drivers implementing
NV_mesh_shader or using nir_lower_multiview on geometry, tessellation,
or mesh shaders. No drivers currently do either of these. There was some
code that attempted to handle the nested per-view case by unwrapping
per-view/arrayed types twice, but it's unclear to what extent this
actually worked.
ANV and Turnip both rely on per-view outputs being assigned a unique
driver location for each view, so I've added on option to configure that
behavior rather than removing it.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31704>
Black Myth Wukong is generating more than 2Gb of shaders in
pre-compiling stage after VK_EXT_shader_image_atomic_int64 extension
enabled. Driver will crash in create shader stages due to dereference
null pointer of kernel map.
Signed-off-by: Mi, Yanfeng <yanfeng.mi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32548>
The last argument seems to be used as brw_shader_reloc::delta (from
brw_add_reloc), and we're unconditionally setting it to 0 here, while
the other place where we handle nir_intrinsic_load_reloc_const_intel
seems to be setting the base appropriately.
I found this by inspection while debugging a bug related to this code,
so I'm not aware of any workloads that get improved by this patch.
Related patches:
- ecbec25e84 ("intel/nir: add reloc delta to load_reloc_const_intel intrinsic")
- 99047451c9 ("intel/fs: add plumbing for embedded samplers")
Fixes: ecbec25e84 ("intel/nir: add reloc delta to load_reloc_const_intel intrinsic")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32531>
The slips-file should use the plural form of skip, otherwise it doesn't
end up being used.
We also had some tests that were supposed to be skipped in the expected
failures. Let's remove them, and add a new failure that should have been
turned into a skip to the list as well.
Fixes: eff8a3517d ("panvk: Enable CI on G610")
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32460>
The texture/sampler reswizzle is implemented to allow AFBC for non
canonical component order formats, but it's enabled regardless of
whether the format supports AFBC.
Limit the reswizzling to only apply to formats that support AFBC.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32515>
The AFBC texture/sample reswizzle will not work for formats with
component orders that are not canonical or RB-swapped, as moving the
alpha channel breaks opaque black border-colors.
Disable AFBC for formats with other component orders than RGB and BGR on
v7.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32515>
There should be no limitation on component order support for AFRC, so
the reswizzling of texture/sampler should not be necessary in this case.
For PanVK, only the texture reswizzling was implemented (with the
equivalent sampler reswizzling missing), so removing it allows us to
pass various border-color tests.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32515>
The spec says:
"
When an image view of a depth/stencil image is used as a
depth/stencil framebuffer attachment, the aspectMask is
ignored and both depth and stencil image subresources are used.
"
Make sure we do that when initializing depth/stencil attachments.
Fixes the
dEQP-VK.renderpass.suballocation.subpass_dependencies.late_fragment_tests.*.subpass_count_*.d24_unorm_s8_uint
dEQP-VK.renderpass.suballocation.subpass_dependencies.late_fragment_tests.*.subpass_count_*.d32_sfloat_s8_uint
failures.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32379>
