Commit Graph

84113 Commits

Author SHA1 Message Date
Jason Ekstrand
ba88a9622d isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
f6c75df083 isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer.  While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
7997f4f95b i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state.  For now, we just use it for the format and the
swizzle.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
e046a46460 i965/blorp: Move intratile offset calculations out of surface state setup
Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that.  Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
27a58615d3 i965/blorp: Refactor interleaved multisample destination handling
We put all of the code for fake IMS together.  This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
3c25caa318 i965/blorp: Get rid of brw_blorp_surface_info::array_layout
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
09879eff30 i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
We also remove brw_blorp_surface_info::msaa_layout.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
e2a1bdb3c5 i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
28b0ad890c i965/blorp: Get rid of brw_blorp_surface_info::num_samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
aa6c058ac4 i965/blorp: Make sample count asserts a bit more lazy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
aa4117a9e4 i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
801189e199 i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
b82de88008 i965/blorp: Create the isl_surf up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ffeb5f67ac i965/blorp/clear: Initialize surface info after allocating an MCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1666d029aa isl/state: Use a valid alignment for 1-D textures
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
0aa0b39769 i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks
It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
573f6ffd04 isl: Fix the parameter names for get_intratile_offset
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Brian Paul
5de29aeef0 util: try to use SSE instructions with MSVC and 32-bit gcc
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient.  This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.

Note, this patch doesn't address the use of SSE4.1 with MSVC.

v2: get rid of the ROUND_WITH_SSE symbol, per Matt.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 12:53:20 -06:00
Brian Paul
18e6e0796a svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()
The function was always returning false because of this typo.

Retested with piglit.  There's some sRGB-related blit failures, but
that seems unrelated.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2016-08-17 12:53:20 -06:00
Brian Paul
55417140cd svga: initialize a variable to silence a gcc warning
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-08-17 12:53:20 -06:00
Ian Romanick
607ab6d3bf glsl: Pull enum ir_expression_operation out to its own file
No change except to the copyright symbol.  The next patch will generate
this file with Python, and Unicode + Python = pure rage.

v2: Massive rebase... I guess a lot can change in a year.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 13:48:25 +01:00
Ian Romanick
de71bc9eb6 glsl: Make the generated sources build rules more like NIR
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 13:48:25 +01:00
Francesco Ansanelli
120c9c6380 mesa/st: use llabs instead of abs for long args (v2)
v2: long has 32bit on Windows (Marek)
Signed-off-by: Francesco Ansanelli <francians@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 14:16:29 +02:00
Marek Olšák
57a8991020 radeonsi: fix up buffer descriptor upper-bound checking
st/mesa does this too, so we're safe.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
325379096f gallium: change pipe_image_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
7cd256ce7e gallium: change pipe_sampler_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
1ac23a9359 gallium/radeon: assign the highest priority to scratch; make rings second
just FYI, the kernel receives priority/4

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:29 +02:00
Marek Olšák
9009516501 gallium/winsys: re-number winsys priority flags
free 60..63, move CP_DMA up

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
95020c6dfd gallium/radeon: mark shader rings as highest-priority buffers
and rename the enum

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
e2bb24f213 gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffers
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
a6b5845a0d radeonsi: use current context for DCC feedback-loop decompress, fixes Elemental
This is just a workaround. The problem is described in the code.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541

v2: say that it's only between the current context and aux_context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
2016-08-17 12:24:35 +02:00
Marek Olšák
9812a50ae6 radeonsi: simplify CB_TARGET_MASK logic
we can now rely on CB_COLORn_INFO to disable empty slots.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
2d2b384066 radeonsi: don't set CB_COLOR1_INFO for dual src blending
Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT
from NI was moved to SPI_SHADER_COL_FORMAT for SI.

I asked CB guys about this 2 days ago and they still haven't replied.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
e722b90bc9 radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound
All VP DX9 ports benefit from this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Marek Olšák
3de8ffe836 gallium/radeon: use unflushed fences for PIPE_QUERY_GPU_FINISHED
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00
Nicolai Hähnle
c5798d6314 gallium/radeon: use lp_build_alloca_undef
Avoid building all those store 0 / store undef instruction pairs that
end up getting removed anyway.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:25 +02:00
Nicolai Hähnle
41001ca4bd gallivm: add lp_build_alloca_undef
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:24 +02:00
Nicolai Hähnle
17e88e276c gallivm: add create_builder_at_entry helper function
Reduces code duplication.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:24 +02:00
Nicolai Hähnle
f4204ba53d gallium/radeon: protect against out of bounds temporary array accesses
They can lead to VM faults and worse, which goes against the GL robustness
promises.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:24 +02:00
Nicolai Hähnle
ea283779be gallium/radeon: add radeon_llvm_bound_index for bounds checking
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:24 +02:00
Nicolai Hähnle
8916d1e2fa gallium/radeon: reduce alloca of temporaries based on usagemask
v2: take actual writemasks into account

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:24 +02:00
Nicolai Hähnle
6bba956073 gallium/radeon: use tgsi_scan_arrays for temp arrays
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
7c2295d7ef gallium/radeon: allocate temps array info in radeon_llvm_context_init
Also, prepare for using tgsi_array_info.

This also opens the door for properly handling allocation failures, but I'm
leaving that for a separate change.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
850c8dcc9c gallium/radeon: always do the full store in store_value_to_array
Doing the write-back of the temporary vector in radeon_llvm_emit_store makes
no sense.

This also allows us to get rid of get_alloca_for_array.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
4b150931c9 gallium/radeon: extract common getelementptr logic into get_pointer_into_array
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
dfbb8ea284 gallium/radeon: pass indirect register info into get_alloca_for_array
To have the same signature as get_array_range.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
b76aabffa2 gallium/radeon: extract common lookup code into get_temp_array function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:23 +02:00
Nicolai Hähnle
fa84296a5a gallium/radeon: clarify the comment on the array alloca heuristic
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:22 +02:00
Nicolai Hähnle
92b66b38c9 gallium/radeon: more descriptive names for LLVM temporaries in debug builds
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:22 +02:00
Nicolai Hähnle
eacfc86d83 gallium/radeon: simplify radeon_llvm_emit_store for direct array addressing
We can use the pointer stored in the temps array directly.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 12:11:22 +02:00