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Author SHA1 Message Date
Jesse Natalie
0069ac9e6e dzn: Disable depth when the rasterizer is disabled due to no position output 
D3D considers the rasterizer enabled if there's a pixel shader *or* if
depth is enabled, since you can do depth-only rendering. After parsing
shaders, if we find that there was supposed to be a pixel shader, but
we removed it because there was no output position, disable depth too.

Also, store this info in the cache, since we might not even load the
nir shaders if we'd seen this pipeline before.

Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
682605a99b dzn: Add a zeroed zsa state when depth or raster is disabled 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
25d460a818 dzn: Always align cached pipeline header size to input element align 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
4565490b71 dzn: Support unnormalized coordinate samplers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
552ab9c2f7 dzn: Support root signature 1.2 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
1e0adac84a dzn: Define a symbol that was present in older D3D headers 
D3D12_BARRIER_SYNC_INPUT_ASSEMBLER was renamed to D3D12_BARRIER_SYNC_INDEX_INPUT,
so conditionally define the old name based on the version of the headers that are
being used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
EmperorPenguin18
3eb33ec9e9 v3d: expose more drm formats with SAND128 modifier 
Adds four more PIPE_FORMATs that expose BROADCOM_SAND128. This allows mpv
to do hardware decoding on the Raspberry Pi 4.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7944
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20510>
 2023-01-17 19:57:28 +00:00
Rob Clark
aac66fe039 freedreno/a6xx: Rework barrier handling 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
63e889516d freedreno: Don't re-install a flushed batch 
The compute path does this save/restore dance with the current batch, so
various things called to emit state can assume ctx->batch is the current
thing.  But during resource tracking, which could have flushed what was
previously the current batch.  Fixes a problem that surfaces in the next
patch when we stop just flushing batches for all the barriers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
aa9b62cad3 freedreno/a6xx: Workaround for no pos/psize 
The hw seems unhappy if there are zero outputs from the last geometry
stage.  So add a dummy varying as a workaround.  Turnip got a similar
workaround in commit d6d75fcd91 ("tu: Fix hangs for DS with no output")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
e41d19a711 freedreno: Fix tracking of enabled SSBOs 
Clearing all of the modified bits an relying on OR'ing the needed bits
back in the loop below doesn't quite work out, Because of early continue
if the SSBO has not changed.

Fixes: 0ed053f03d ("freedreno: simplify fd_set_shader_buffers(..)")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
ca2011d11c freedreno/drm: Remove assert 
We can hit this scenario if there is a GPU hang before the userspace
fence writeback happens.  Since we have asserts enabled in CI, just
remove this assert.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Gert Wollny
adee0e7e53 r600/sfn: Do a bit of cleanup with the secondary read port validation 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
 2023-01-17 19:19:01 +00:00
Gert Wollny
ca5bbff558 r600/sfn: Fix readport check 
We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.

For clarity also rename the bank swizzle iterator iterator.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
 2023-01-17 19:19:01 +00:00
Rhys Perry
42d51ef2bb radv/gfx11: expose shaderBufferFloat32AtomicAdd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
7dd16791ca radv: load ssbo_atomic_fadd descriptor 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
068c84f275 aco: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
ea1ac3901a ac/llvm: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
José Roberto de Souza
e879b28994 anv: Move anv_device_check_status() code to i915/anv_device.c 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94af444490 anv: Split i915 code from anv_batch_chain.c 
There is no change in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94ca73b356 anv: Export anv_exec_batch_debug() and chain_command_buffers() 
This functions will be used by i915 and Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
80c89c4606 anv: Start to move i915 specific code from anv_device to i915/anv_device 
More code re-organization to separate i915_drm.h specific code from
the rest.

No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
Gert Wollny
8084b412ca virgl: drop the separable flag for cases that can't be handled 
The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.

v2: skip tests for VS input and FS outputs

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>
 2023-01-17 16:58:52 +00:00
Rob Clark
aa7c83786d freedreno/ci: Add an a618 flake 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
a7a46556ec Revert "freedreno/ci: Switch a630 jobs over to manual" 
This reverts commit 0cc3701338.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
23e6d0ce79 Revert "freedreno/ci: Switch also performance a630 job to manual" 
This reverts commit 3be7a28b24.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Lionel Landwerlin
f9115b6d51 intel: use a shared UUID with other drivers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>
 2023-01-17 17:36:07 +02:00
Tapani Pälli
53de48f1c4 intel/compiler: add cpp_std=c++17 when building tests 
Otherwise build fails:

"../src/intel/compiler/brw_private.h:40:4: note:
 ‘std::variant’ is only available from C++17 onwards"

Fixes: 6c194ddd18 ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>
 2023-01-17 13:58:03 +00:00
Gert Wollny
d59e5aa08f virgl: Request setting the atomic offset in the range_base 
With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.

Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
994cf0e995 virgl: lower image variable offsets into the intrinsic range_base value 
With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.

Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
7380656a8c ntt: Make use of the range_base offset when translating atomics in NTT 
v2: Unconditionally add teh range base, it is properly initialized.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
36f19058ae ntt: handle the image intrinsic range_base when translating to TGSI 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
2e05cfa179 nir: Add range_base to atomic_counter and an option to use it 
Some drivers may encode constant offsets in the instruction, so
make it possible for the drivers to request lowering the atomic
uniform offset into the range_base variable of the intrinsic.

v2: drop patch to use build-in array offset evaluation, it makes
    problems with zink, and update the code accordingly
v3: always initialize range base

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
c4cde91c1b nir: Add possibility to store image var offset in range_base 
Add the intrinsic range_base value to the image intrinsics and add
the option to store the image array offset into range_base instead
of adding it to the image array index if the driver requests it.

v2: Always initialize range_base

v3: fix for bindless intrinsics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Jesse Natalie
2f4c7b5ccf dzn: Use typeless format for creation of depth-only or stencil-only D24S8 
When querying capabilities or creating views using a scoped aspect
mask, we want to return the format for the correct single-channel
format, but when actually creating the resource (aspect mask 0),
we want to use the typeless format, since the single-channel formats
don't report multisampling support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
9f928adf81 dzn: Set MultisampleEnable to enable MSAA lines 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
ca20577622 dzn: Storage buffer sizes need to be 4-byte-aligned 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
b948a5db4f dzn: Support int border colors 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
10282bbd96 dzn: Use R24G8_TYPELESS for 24/8 depth resources 
This is the same that was already being done for R32G8X24, not sure
why it was missed for R24G8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
a3005ecb56 dzn: When changing root signature, dirty descriptors too 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
14f0c85874 dzn: Support alpha blend factor 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
aa3fc8753d dzn: Get options13 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
22eb9b1c12 spirv2dxil: Replace not-provided inputs with zero instead of undef 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
61c391781e spirv2dxil: Allow killing position as an undef varying 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
3ddf41cb7d spirv2dxil: When removing unused inputs, make sure they're actually inputs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
00b9c10cf7 spirv2dxil: For removing unused vars, consider the whole I/O var size 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
85f44304d8 microsoft/compiler: Set num_components to 4 when updating pos write instructions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
5d8e89f92f microsoft/compiler: Use nir info.fs.uses_sample_shading to force sample-rate 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
cbc481f39f microsoft/compiler: Re-work the logic for adding SV_SampleIndex to force sample-rate 
Only add SV_SampleIndex if there exists a sample-rate var that has either flat
interpolation or centroid (and therefore can't force sample rate implicitly),
unless there is also a sample-rate var that doesn't have those properties.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
b151ed4b95 microsoft/compiler: Always emit float types in the I/O signature for structs 
There's VK tests that have mismatching interpolation specifiers between FS
and the previous stage. For structs, that resulted in different types, which
breaks DXIL validation.

We could link the shaders and have that overwrite the interpolation field from
the previous shader, but we could also just not care and always use float.
I don't see any regressions from that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00