From ff816f224b8131180bc0d4bf41a91fdb97079710 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 29 Aug 2023 14:57:44 -0400 Subject: [PATCH] agx: Split nest instruction into begin_cf + break We use it for two different things. Pseudo-instructions are cheap, split it up for easier optimization passes. This also fixes the schedule classes.. we can move the cf_begin around if we want, it's inert. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_compile.c | 7 ++----- src/asahi/compiler/agx_compiler.h | 1 + src/asahi/compiler/agx_lower_pseudo.c | 9 +++++++-- src/asahi/compiler/agx_opcodes.py | 7 ++++--- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index cfa6212f227..d469c104af0 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -1752,10 +1752,7 @@ agx_emit_jump(agx_builder *b, nir_jump_instr *instr) agx_block_add_successor(ctx->current_block, ctx->break_block); } - /* Update the counter and flush */ - agx_nest(b, nestings); - agx_pop_exec(b, 0); - + agx_break(b, nestings); ctx->current_block->unconditional_jumps = true; } @@ -1999,7 +1996,7 @@ emit_first_cf(agx_context *ctx) return; agx_builder _b = agx_init_builder(ctx, agx_after_block(ctx->current_block)); - agx_nest(&_b, 0); + agx_begin_cf(&_b); ctx->any_cf = true; } diff --git a/src/asahi/compiler/agx_compiler.h b/src/asahi/compiler/agx_compiler.h index ec3437d385d..b38c43a99bc 100644 --- a/src/asahi/compiler/agx_compiler.h +++ b/src/asahi/compiler/agx_compiler.h @@ -695,6 +695,7 @@ instr_after_logical_end(const agx_instr *I) case AGX_OPCODE_JMP_EXEC_ANY: case AGX_OPCODE_JMP_EXEC_NONE: case AGX_OPCODE_POP_EXEC: + case AGX_OPCODE_BREAK: case AGX_OPCODE_IF_ICMP: case AGX_OPCODE_WHILE_ICMP: case AGX_OPCODE_IF_FCMP: diff --git a/src/asahi/compiler/agx_lower_pseudo.c b/src/asahi/compiler/agx_lower_pseudo.c index 73b1dcf884d..8087c199c71 100644 --- a/src/asahi/compiler/agx_lower_pseudo.c +++ b/src/asahi/compiler/agx_lower_pseudo.c @@ -5,6 +5,7 @@ #include "agx_builder.h" #include "agx_compiler.h" +#include "agx_opcodes.h" /* Lower pseudo instructions created during optimization. */ static agx_instr * @@ -29,8 +30,12 @@ lower(agx_builder *b, agx_instr *I) return agx_bitop_to(b, I->dest[0], I->src[0], I->src[1], AGX_BITOP_OR); /* Writes to the nesting counter lowered to the real register */ - case AGX_OPCODE_NEST: - return agx_mov_imm_to(b, agx_register(0, AGX_SIZE_16), I->imm); + case AGX_OPCODE_BEGIN_CF: + return agx_mov_imm_to(b, agx_register(0, AGX_SIZE_16), 0); + + case AGX_OPCODE_BREAK: + agx_mov_imm_to(b, agx_register(0, AGX_SIZE_16), I->nest); + return agx_pop_exec(b, 0); default: return NULL; diff --git a/src/asahi/compiler/agx_opcodes.py b/src/asahi/compiler/agx_opcodes.py index 71a9a45a5fa..109435f6d9c 100644 --- a/src/asahi/compiler/agx_opcodes.py +++ b/src/asahi/compiler/agx_opcodes.py @@ -420,6 +420,7 @@ op("unit_test", _, dests = 0, srcs = 1, can_eliminate = False) # to be coalesced during RA, rather than lowered to a real move. op("preload", _, srcs = 1, schedule_class = "preload") -# Set the nesting counter. Lowers to mov_imm r0l, #nest after RA. -op("nest", _, dests = 0, imms = [IMM], can_eliminate = False, - schedule_class = "barrier") +# Pseudo-instructions to set the nesting counter. Lowers to r0l writes after RA. +op("begin_cf", _, dests = 0, can_eliminate = False) +op("break", _, dests = 0, imms = [NEST], can_eliminate = False, + schedule_class = "invalid")