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intel/compiler: Don't store "scalar stage" bits on Gfx8 or Gfx9

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Since 1d71b1a311, only Gfx7 and earlier have any vec4 stages ever.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14128>
This commit is contained in:
Ian Romanick
2021-10-08 12:09:04 -07:00
parent 4563261ad1
commit ff74d5dd1b
1 changed files with 1 additions and 6 deletions
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7
src/intel/compiler/brw_compiler.c
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@@ -206,12 +206,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
{ {
uint64_t config = 0; uint64_t config = 0;
insert_u64_bit(&config, compiler->precise_trig); insert_u64_bit(&config, compiler->precise_trig);
if (compiler->devinfo->ver >= 8 && compiler->devinfo->ver < 10) {
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
}
uint64_t mask = DEBUG_DISK_CACHE_MASK; uint64_t mask = DEBUG_DISK_CACHE_MASK;
while (mask != 0) { while (mask != 0) {
const uint64_t bit = 1ULL << (ffsll(mask) - 1); const uint64_t bit = 1ULL << (ffsll(mask) - 1);