OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

genxml/hsw: Add L3 cache control registers

Browse Source 
These were added to the i965 driver in
5912da45a6.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jordan Justen
2016-04-02 01:25:05 -07:00
parent 47b390fe45
commit ff41738871
1 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/intel/genxml/gen75.xml
View File

@@ -2932,4 +2932,12 @@
<field name="T Low Bandwidth" start="21" end="21" type="uint"/>
</register>
<register name="SCRATCH1" length="1" num="0xb038">
<field name="L3 Atomic Disable" start="27" end="27" type="uint"/>
</register>
<register name="CHICKEN3" length="1" num="0xe49c">
<field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
</register>
</genxml>