Implement ARB_f_p KIL correctly.
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@@ -95,7 +95,7 @@ static const struct instruction_pattern Instructions[] = {
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{ "EX2", FP_OPCODE_DP4, INPUT_1S, OUTPUT_S, _R | _H | _C | _S },
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{ "EX2", FP_OPCODE_DP4, INPUT_1S, OUTPUT_S, _R | _H | _C | _S },
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{ "FLR", FP_OPCODE_FLR, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
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{ "FLR", FP_OPCODE_FLR, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
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{ "FRC", FP_OPCODE_FRC, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
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{ "FRC", FP_OPCODE_FRC, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
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{ "KIL", FP_OPCODE_KIL, INPUT_CC, OUTPUT_NONE, 0 },
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{ "KIL", FP_OPCODE_KIL_NV, INPUT_CC, OUTPUT_NONE, 0 },
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{ "LG2", FP_OPCODE_LG2, INPUT_1S, OUTPUT_S, _R | _H | _C | _S },
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{ "LG2", FP_OPCODE_LG2, INPUT_1S, OUTPUT_S, _R | _H | _C | _S },
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{ "LIT", FP_OPCODE_LIT, INPUT_1V, OUTPUT_V, _R | _H | _C | _S },
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{ "LIT", FP_OPCODE_LIT, INPUT_1V, OUTPUT_V, _R | _H | _C | _S },
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{ "LRP", FP_OPCODE_LRP, INPUT_3V, OUTPUT_V, _R | _H | _X | _C | _S },
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{ "LRP", FP_OPCODE_LRP, INPUT_3V, OUTPUT_V, _R | _H | _X | _C | _S },
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@@ -1291,7 +1291,7 @@ Parse_InstructionSequence(struct parse_state *parseState,
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RETURN_ERROR1("Expected ,");
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RETURN_ERROR1("Expected ,");
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}
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}
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else if (instMatch.outputs == OUTPUT_NONE) {
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else if (instMatch.outputs == OUTPUT_NONE) {
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ASSERT(instMatch.opcode == FP_OPCODE_KIL);
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ASSERT(instMatch.opcode == FP_OPCODE_KIL_NV);
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/* This is a little weird, the cond code info is in the dest register */
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/* This is a little weird, the cond code info is in the dest register */
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if (!Parse_CondCodeMask(parseState, &inst->DstReg))
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if (!Parse_CondCodeMask(parseState, &inst->DstReg))
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RETURN_ERROR;
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RETURN_ERROR;
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@@ -75,7 +75,8 @@ enum fp_opcode {
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FP_OPCODE_EX2,
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FP_OPCODE_EX2,
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FP_OPCODE_FLR,
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FP_OPCODE_FLR,
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FP_OPCODE_FRC,
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FP_OPCODE_FRC,
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FP_OPCODE_KIL,
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FP_OPCODE_KIL_NV, /* NV_f_p only */
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FP_OPCODE_KIL, /* ARB_f_p only */
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FP_OPCODE_LG2,
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FP_OPCODE_LG2,
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FP_OPCODE_LIT,
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FP_OPCODE_LIT,
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FP_OPCODE_LRP,
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FP_OPCODE_LRP,
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@@ -763,7 +763,7 @@ execute_program( GLcontext *ctx,
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store_vector4( inst, machine, result );
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store_vector4( inst, machine, result );
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}
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}
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break;
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break;
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case FP_OPCODE_KIL:
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case FP_OPCODE_KIL_NV: /* NV_f_p only */
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{
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{
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const GLuint *swizzle = inst->DstReg.CondSwizzle;
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const GLuint *swizzle = inst->DstReg.CondSwizzle;
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const GLuint condMask = inst->DstReg.CondMask;
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const GLuint condMask = inst->DstReg.CondMask;
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@@ -775,6 +775,15 @@ execute_program( GLcontext *ctx,
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}
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}
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}
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}
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break;
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break;
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case FP_OPCODE_KIL: /* ARB_f_p only */
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{
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GLfloat a[4];
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fetch_vector4( ctx, &inst->SrcReg[0], machine, program, a );
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if (a[0] < 0.0F || a[1] < 0.0F || a[2] < 0.0F || a[3] < 0.0F) {
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return GL_FALSE;
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}
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}
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break;
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case FP_OPCODE_LG2: /* log base 2 */
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case FP_OPCODE_LG2: /* log base 2 */
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{
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{
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GLfloat a[4], result[4];
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GLfloat a[4], result[4];
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