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intel/compiler/xe2: Handle new URB write messages

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Rework:
 * idr v1: Fix compilation error.
 * idr v2: Add support for per-channel offsets.
 * idr v3: get_lowered_simd_width is 16 on Xe2+.
 * idr v4: Add disassembly support.  Add validation support.
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
This commit is contained in:
Ian Romanick
2022-07-20 10:21:21 -07:00
committed by Marge Bot
parent fa53a7d241
commit feec9166cd
4 changed files with 234 additions and 36 deletions
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6
src/intel/compiler/brw_eu_validate.c
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@@ -2485,6 +2485,10 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
const uint32_t desc = brw_inst_send_desc(devinfo, inst);
switch (brw_inst_sfid(devinfo, inst)) {
case BRW_SFID_URB:
if (devinfo->ver < 20)
break;
FALLTHROUGH;
case GFX12_SFID_TGM:
case GFX12_SFID_SLM:
case GFX12_SFID_UGM:
@@ -2500,7 +2504,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
break;
}
if (brw_inst_sfid(devinfo, inst) == BRW_SFID_URB) {
if (brw_inst_sfid(devinfo, inst) == BRW_SFID_URB && devinfo->ver < 20) {
/* Gfx4 doesn't have a "header present" bit in the SEND message. */
ERROR_IF(devinfo->ver > 4 && !brw_inst_header_present(devinfo, inst),
"Header must be present for all URB messages.");