pan/bi: Fix spilling on Valhall
We need a slightly different idiom on Valhall, since the segment modifiers no longer exist but we now have an immediate offset. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15793>
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@@ -479,12 +479,18 @@ bi_count_read_index(bi_instr *I, bi_index index)
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* for the target, so the spill/fill code becomes architecture-independent.
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*/
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static bi_index
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bi_tls_ptr(bool hi)
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{
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return bi_fau(BIR_FAU_TLS_PTR, hi);
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}
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static bi_instr *
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bi_load_tl(bi_builder *b, unsigned bits, bi_index src, unsigned offset)
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{
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if (b->shader->arch >= 9) {
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return bi_load_to(b, bits, src, va_zero_lut(), va_zero_lut(),
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BI_SEG_TL, offset);
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return bi_load_to(b, bits, src, bi_tls_ptr(false),
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bi_tls_ptr(true), BI_SEG_TL, offset);
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} else {
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return bi_load_to(b, bits, src, bi_imm_u32(offset), bi_zero(),
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BI_SEG_TL, 0);
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@@ -495,7 +501,7 @@ static void
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bi_store_tl(bi_builder *b, unsigned bits, bi_index src, unsigned offset)
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{
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if (b->shader->arch >= 9) {
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bi_store(b, bits, src, va_zero_lut(), va_zero_lut(), BI_SEG_TL, offset);
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bi_store(b, bits, src, bi_tls_ptr(false), bi_tls_ptr(true), BI_SEG_TL, offset);
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} else {
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bi_store(b, bits, src, bi_imm_u32(offset), bi_zero(), BI_SEG_TL, 0);
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}
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