radeonsi: fix future C++ compile failures and warnings
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7807>
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@@ -264,12 +264,11 @@ static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned
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unsigned *value, unsigned *saved_val, unsigned num)
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{
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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int i, j;
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for (i = 0; i < num; i++) {
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for (unsigned i = 0; i < num; i++) {
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if (saved_val[i] != value[i]) {
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radeon_set_context_reg_seq(cs, offset, num);
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for (j = 0; j < num; j++)
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for (unsigned j = 0; j < num; j++)
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radeon_emit(cs, value[j]);
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memcpy(saved_val, value, sizeof(uint32_t) * num);
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@@ -50,10 +50,10 @@ extern "C" {
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* one which will mean "unknown" for the purpose of state tracking and
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* the number shouldn't be a commonly-used one. */
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#define SI_BASE_VERTEX_UNKNOWN INT_MIN
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#define SI_START_INSTANCE_UNKNOWN INT_MIN
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#define SI_DRAW_ID_UNKNOWN INT_MIN
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#define SI_RESTART_INDEX_UNKNOWN INT_MIN
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#define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
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#define SI_START_INSTANCE_UNKNOWN ((unsigned)INT_MIN)
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#define SI_DRAW_ID_UNKNOWN ((unsigned)INT_MIN)
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#define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN)
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#define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN)
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#define SI_NUM_SMOOTH_AA_SAMPLES 8
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#define SI_MAX_POINT_SIZE 2048
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#define SI_GS_PER_ES 128
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@@ -1106,17 +1106,17 @@ struct si_context {
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bool ngg : 1;
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bool same_patch_vertices : 1;
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uint8_t ngg_culling;
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int last_index_size;
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unsigned last_index_size;
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int last_base_vertex;
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int last_start_instance;
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int last_instance_count;
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int last_drawid;
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int last_sh_base_reg;
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unsigned last_start_instance;
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unsigned last_instance_count;
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unsigned last_drawid;
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unsigned last_sh_base_reg;
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int last_primitive_restart_en;
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int last_restart_index;
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int last_prim;
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int last_multi_vgt_param;
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int last_gs_out_prim;
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unsigned last_restart_index;
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unsigned last_prim;
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unsigned last_multi_vgt_param;
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unsigned last_gs_out_prim;
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int last_binning_enabled;
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unsigned current_vs_state;
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unsigned last_vs_state;
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@@ -1140,11 +1140,11 @@ struct si_context {
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/* Local shader (VS), or HS if LS-HS are merged. */
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struct si_shader *last_ls;
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struct si_shader_selector *last_tcs;
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int last_num_tcs_input_cp;
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int last_tes_sh_base;
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unsigned last_num_tcs_input_cp;
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unsigned last_tes_sh_base;
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bool last_tess_uses_primid;
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unsigned last_num_patches;
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int last_ls_hs_config;
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unsigned last_ls_hs_config;
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/* Debug state. */
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bool is_debug;
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@@ -443,7 +443,7 @@ struct si_shader_selector {
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unsigned ngg_cull_nonindexed_fast_launch_vert_threshold; /* UINT32_MAX = disabled */
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ubyte clipdist_mask;
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ubyte culldist_mask;
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ubyte rast_prim;
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enum pipe_prim_type rast_prim;
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/* ES parameters. */
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uint16_t esgs_itemsize; /* vertex stride */
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@@ -1697,7 +1697,8 @@ static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_d
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unsigned *data;
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if (indirect->indirect_draw_count) {
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data = pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count,
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data = (unsigned*)
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pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count,
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indirect->indirect_draw_count_offset, sizeof(unsigned),
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PIPE_MAP_READ, &transfer);
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@@ -1714,7 +1715,8 @@ static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_d
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}
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map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
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data = pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size,
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data = (unsigned*)
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pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size,
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PIPE_MAP_READ, &transfer);
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begin = UINT_MAX;
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@@ -1797,15 +1799,18 @@ static bool si_all_vs_resources_read_only(struct si_context *sctx, struct pipe_r
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{
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struct radeon_winsys *ws = sctx->ws;
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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struct si_descriptors *buffers =
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&sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
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struct si_shader_selector *vs = sctx->vs_shader.cso;
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struct si_vertex_elements *velems = sctx->vertex_elements;
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unsigned num_velems = velems->count;
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unsigned num_images = vs->info.base.num_images;
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/* Index buffer. */
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if (indexbuf && ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf, RADEON_USAGE_WRITE))
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goto has_write_reference;
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/* Vertex buffers. */
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struct si_vertex_elements *velems = sctx->vertex_elements;
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unsigned num_velems = velems->count;
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for (unsigned i = 0; i < num_velems; i++) {
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if (!((1 << i) & velems->first_vb_use_mask))
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continue;
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@@ -1820,8 +1825,6 @@ static bool si_all_vs_resources_read_only(struct si_context *sctx, struct pipe_r
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}
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/* Constant and shader buffers. */
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struct si_descriptors *buffers =
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&sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
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for (unsigned i = 0; i < buffers->num_active_slots; i++) {
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unsigned index = buffers->first_active_slot + i;
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struct pipe_resource *res = sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
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@@ -1833,7 +1836,6 @@ static bool si_all_vs_resources_read_only(struct si_context *sctx, struct pipe_r
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}
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/* Samplers. */
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struct si_shader_selector *vs = sctx->vs_shader.cso;
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if (vs->info.base.textures_used) {
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unsigned num_samplers = util_last_bit(vs->info.base.textures_used);
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@@ -1848,7 +1850,6 @@ static bool si_all_vs_resources_read_only(struct si_context *sctx, struct pipe_r
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}
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/* Images. */
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unsigned num_images = vs->info.base.num_images;
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if (num_images) {
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for (unsigned i = 0; i < num_images; i++) {
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struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
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