spirv: add support for SPV_AMD_shader_trinary_minmax
Co-authored-by: Daniel Schürmann <daniel.schuermann@campus.tu-berlin.de> Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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committed by
Bas Nieuwenhuizen

parent
3e830a1af2
commit
fe5d5d19b0
@@ -52,6 +52,7 @@ struct spirv_supported_capabilities {
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bool subgroup_shuffle;
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bool subgroup_vote;
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bool gcn_shader;
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bool trinary_minmax;
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};
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typedef struct shader_info {
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@@ -378,6 +378,9 @@ vtn_handle_extension(struct vtn_builder *b, SpvOp opcode,
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} else if ((strcmp((const char *)&w[2], "SPV_AMD_gcn_shader") == 0)
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&& (b->options && b->options->caps.gcn_shader)) {
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val->ext_handler = vtn_handle_amd_gcn_shader_instruction;
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} else if ((strcmp((const char *)&w[2], "SPV_AMD_shader_trinary_minmax") == 0)
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&& (b->options && b->options->caps.trinary_minmax)) {
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val->ext_handler = vtn_handle_amd_shader_trinary_minmax_instruction;
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} else {
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vtn_fail("Unsupported extension");
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}
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@@ -55,3 +55,55 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, uint32_t ext_opcode
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}
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return true;
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}
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bool
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vtn_handle_amd_shader_trinary_minmax_instruction(struct vtn_builder *b, uint32_t ext_opcode,
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const uint32_t *w, unsigned count)
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{
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struct nir_builder *nb = &b->nb;
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const struct glsl_type *dest_type =
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vtn_value(b, w[1], vtn_value_type_type)->type->type;
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struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
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val->ssa = vtn_create_ssa_value(b, dest_type);
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unsigned num_inputs = count - 5;
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assert(num_inputs == 3);
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nir_ssa_def *src[3] = { NULL, };
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for (unsigned i = 0; i < num_inputs; i++)
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src[i] = vtn_ssa_value(b, w[i + 5])->def;
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switch ((enum ShaderTrinaryMinMaxAMD)ext_opcode) {
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case FMin3AMD:
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val->ssa->def = nir_fmin3(nb, src[0], src[1], src[2]);
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break;
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case UMin3AMD:
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val->ssa->def = nir_umin3(nb, src[0], src[1], src[2]);
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break;
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case SMin3AMD:
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val->ssa->def = nir_imin3(nb, src[0], src[1], src[2]);
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break;
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case FMax3AMD:
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val->ssa->def = nir_fmax3(nb, src[0], src[1], src[2]);
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break;
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case UMax3AMD:
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val->ssa->def = nir_umax3(nb, src[0], src[1], src[2]);
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break;
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case SMax3AMD:
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val->ssa->def = nir_imax3(nb, src[0], src[1], src[2]);
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break;
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case FMid3AMD:
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val->ssa->def = nir_fmed3(nb, src[0], src[1], src[2]);
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break;
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case UMid3AMD:
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val->ssa->def = nir_umed3(nb, src[0], src[1], src[2]);
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break;
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case SMid3AMD:
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val->ssa->def = nir_imed3(nb, src[0], src[1], src[2]);
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break;
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default:
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unreachable("unknown opcode\n");
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break;
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}
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return true;
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}
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@@ -735,4 +735,6 @@ vtn_u64_literal(const uint32_t *w)
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bool vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, uint32_t ext_opcode,
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const uint32_t *words, unsigned count);
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bool vtn_handle_amd_shader_trinary_minmax_instruction(struct vtn_builder *b, uint32_t ext_opcode,
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const uint32_t *words, unsigned count);
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#endif /* _VTN_PRIVATE_H_ */
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