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freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs

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The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the
second part for sysvals.

The sysvals don't need to be pre-assigned since the state for those isn't
shared between binning / nonbinning shaders.

Fixes assert failures in cases where the sysvals didn't end up in the same
registers for binning / nonbinning.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
This commit is contained in:
Jonathan Marek
2019-12-19 10:40:35 -05:00
parent 2add63060b
commit fe4a8df9a8
1 changed files with 1 additions and 1 deletions
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2
src/freedreno/ir3/ir3_compiler_nir.c
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@@ -3495,7 +3495,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
assert(in->opc == OPC_META_INPUT);
unsigned inidx = in->input.inidx;
if (pre_assign_inputs) {
if (pre_assign_inputs && !so->inputs[inidx].sysval) {
if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
compile_assert(ctx, in->regs[0]->num ==
so->nonbinning->inputs[inidx].regid);