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intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-10-10 18:05:13 -07:00
committed by Jordan Justen
parent 791d040104
commit fe3d90aedf
1 changed files with 4 additions and 3 deletions
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7
src/intel/compiler/brw_fs_reg_allocate.cpp
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@@ -1267,9 +1267,10 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
* exceeding the maximum number of (fake) MRF registers reserved for
* spills.
*/
const unsigned width = 8 * MIN2(
DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE),
spill_max_size(fs));
const unsigned width = 8 * reg_unit(devinfo) *
DIV_ROUND_UP(MIN2(inst->dst.component_size(inst->exec_size),
spill_max_size(fs) * REG_SIZE),
reg_unit(devinfo) * REG_SIZE);
/* Spills should only write data initialized by the instruction for
* whichever channels are enabled in the execution mask. If that's